View KSZ8841-16MVIL_6941258.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ksz8841-16/32mql/mvl/mvli/mbl single-port ethernet mac controller with non-pci interface rev. 1.6 linkmd is a registered trademark of micrel, inc. magic packet is a trademark of advanced micro devices, inc. product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com october 2007 m9999-102207-1.6 general description the ksz8841-series single-port chip includes pci and non-pci cpu interfaces, and are available in 8/16-bit and 32-bit bus designs. this datasheet describes the ksz8841m-series of non-pci cpu interface chips. for information on the ksz8841 pci cpu interface chips, refer to the ksz8841p datasheet. the ksz8841m is a single chip, mixed analog/digital device offering wake-on-lan technology for effectively addressing fast ethernet applications. it consists of a fast ethernet mac controller, an 8-bit, 16-bit, and 32-bit generic host processor interface and incorporates a unique dynamic memory pointer with 4-byte buffer boundary and a fully utilizable 8kb for both tx and rx directions in host buffer interface. the ksz8841m is designed to be fully compliant with the appropriate ieee 802.3 standards. an industrial temperature-grade version of the ksz8841m, the ksz8841mvli, also can be ordered (see ?ordering information section). linkmd ? physical signal transmission and reception are enhanced through the use of analog circuitry, making the design more efficient and allowing for lower-power consumption. the ksz8841m is designed using a low-power cmos process that features a single 3.3v power supply with 5v tolerant i/o. it has an extensive feature set that offers management information base (mib) counters and cpu control/data interfaces. the ksz8841m includes a unique cable diagnostics feature called linkmd ? . this feature determines the length of the cabling plant and also ascertains if there is an open or short condition in the cable. accompanying software enables the cable length and cable conditions to be conveniently displayed. in addition, the ksz8841m supports hewlett packard (hp) auto-mdix thereby eliminating the need to differentiate between straight or crossover cables in applications. functional diagram p1 hp auto m d i/m d i-x host mac 10/100 base-t/tx phy eeprom in te rfa c e led driver mib counters p1 led[3:0] eeprom i/f non-pci cpu bus in te rfa c e unit em bedded processor in te rfa c e qmu dma channel control registers 8,16, or 32-bit g eneric h o s t in te rfa c e rxq 4kb txq 4kb figure 1. ksz8841m functional diagram
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 2 m9999-102207-1.6 features ? single chip ethernet controller with ieee802.3u support ? supports 10base-t/100base-tx ? supports ieee 802.3x full-duplex flow control and half-duplex backpressure collision flow control ? supports burst data transfers ? 8kb internal memory for rx/tx fifo buffers ? early tx/rx functions to minimize latency through the device ? optional to use external serial eeprom configuration for both ksz8841-16mql and ksz8841-32mql ? single 25mhz reference clock for both phy and mac network features ? fully integrated to comply with ieee802.3u standards ? 10base-t and 100base-tx physical layer support ? auto-negotiation: 10/100mbps full and half duplex ? adaptive equalizer ? baseline wander correction power modes, power supplies, and packaging ? single power supply (3.3v) with 5v tolerant i/o buffers ? enhanced power management feature with power- down feature to ensure low-power dissipation during device idle periods ? comprehensive led indicator support for link, activity, full/half duplex, and 10/100 speed (4 leds) ? user programmable ? low-power cmos design ? commercial temperature range: 0 o c to +70 o c ? industrial temperature range: ?40 o c to +85 o c ? available in 128-pin pqfp and 100-ball lfbga (128- pin lqfp optional) additional features in addition to offering all of the features of a layer 2 controller, the ksz8841m offers: ? dynamic buffer memory scheme ? essential for applications such as video over ip where image jitter is unacceptable ? flexible 8-bit, 16-bit, and 32-bit generic host processor interfaces ? micrel linkmd? cable diagnostic capabilities to determine cable length, diagnose faulty cables, and determine distance to fault ? wake-on-lan functionality ? incorporates magic packet?, network link state, and wake-up frame technology ? hp auto mdi-x? crossover with disable/enable option ? ability to transmit and receive frames up to 1916 bytes applications ? video distribution systems ? high-end cable, satellite, and ip set-top boxes ? video over ip ? voice over ip (voip) and analog telephone adapters (ata) ? industrial control in latency critical applications ? motion control ? industrial control sensor devices (temperature, pressure, levels, and valves) ? security and surveillance cameras markets ? fast ethernet ? embedded ethernet ? industrial ethernet
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 3 m9999-102207-1.6 ordering information part number temperature range package ksz8841-16mql 0 o c to 70 o c 128-pin pqfp ksz8841-32mql 0 o c to 70 o c 128-pin pqfp ksz8841-16mvl 0 o c to 70 o c 128-pin lqfp ksz8841-32mvl 0 o c to 70 o c 128-pin lqfp ksz8841-16mvli ?40 o c to +85 o c 128-pin lqfp ksz8841-32mvli ?40 o c to +85 o c 128-pin lqfp ksz8841-16mbl 0 o c to 70 o c 100-ball lfbga ksz8841-16mbli ?40 o c to +85 o c 100-ball lfbga ksz8841-16mql-eval evaluation board for the ksz8841-16mql ksz8841-16mbl-eval evaluation board for the ksz8841-16mbl revision history revision date summary of changes 1.0 06/30/05 first released preliminary information. 1.1 08/08/05 updated general description, functional diagram, pin description and features. added this revision history table and loopback support sections. 1.2 10/04/05 update power saving bit description in p1phyctrl and p1scslmd registers. 1.3 11/01/05 updated figure 12/13/14 asynchronous timing and table 16/17/18 parameters, pqfp package information. 1.4 03/31/06 added qmu rx flow control high watermark qrfcr register and updated body text 1.5 4/10/07 improve the ardy low time in read cycle to 40 ns and in write cycle to 50 ns during qmu data register access 1.6 10/22/07 add ksz8841-16mbl 100-ball bga package information
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 4 m9999-102207-1.6 contents general description ............................................................................................................ .................................................. 1 functional di agram............................................................................................................. .................................................. 1 features ....................................................................................................................... .......................................................... 2 network features ............................................................................................................... ............................................ 2 power modes, power supplies, and packaging..................................................................................... ........................ 2 applicat ions................................................................................................................... ........................................................ 2 markets........................................................................................................................ ........................................................... 2 ordering info rmation ........................................................................................................... ................................................. 3 revision hi story ............................................................................................................... ..................................................... 3 pin configuration for ksz 8841-16 chip (8/16-bit) ............................................................................... ............................ 10 ball configuration for ksz 8841-16 chip (8/16-bit) .............................................................................. ............................ 11 pin description for ksz8841-16 chip (8/16-bit) ................................................................................. .............................. 12 ball description for ksz8841-16 chip (8/16-bit) ................................................................................ .............................. 17 pin configuration for ks z8841-32 chip (32-bit) ................................................................................. ............................. 21 pin description for ksz8841-32 chip (32-bit) ................................................................................... ............................... 22 functional desc ription ......................................................................................................... .............................................. 27 functional ov erview ............................................................................................................ ............................................... 27 power management ............................................................................................................... ...................................... 27 power down ..................................................................................................................... .......................................................... 27 wake-on-lan.................................................................................................................... ......................................................... 27 link change.................................................................................................................... ........................................................... 27 wake-up packet................................................................................................................. ........................................................ 27 magic pa cket................................................................................................................... ........................................................... 27 physical layer transceiver (phy)............................................................................................... ................................. 28 100base-tx transmit............................................................................................................ ................................................... 28 100base-tx receive............................................................................................................. ................................................... 29 pll clock synthesizer (recovery)............................................................................................... .............................................. 29 scrambler/de-scrambler (100base-tx only) ....................................................................................... .................................... 29 10base-t transmit .............................................................................................................. ..................................................... 29 10base-t receive ............................................................................................................... ..................................................... 29 mdi/mdi-x auto crossover....................................................................................................... ................................................. 29 straight cable................................................................................................................. ....................................................... 30 crossover cable................................................................................................................ .................................................... 30 auto negotiation............................................................................................................... .......................................................... 31 linkmd cable diagnostics ....................................................................................................... .................................................. 32 acce ss......................................................................................................................... .......................................................... 32 usage .......................................................................................................................... .......................................................... 32 media access control (mac) operation ........................................................................................... ........................... 32 inter packet gap (ipg)......................................................................................................... ...................................................... 32 back-off algorithm ............................................................................................................. ........................................................ 32 late collision................................................................................................................. ............................................................. 32 flow control................................................................................................................... ............................................................ 32 half-duplex backpressure ....................................................................................................... .................................................. 33 clock generator ................................................................................................................ ......................................................... 33 bus interface unit (biu)....................................................................................................... ......................................... 33 supported transfers ............................................................................................................ ...................................................... 33 physical data bus size ......................................................................................................... ..................................................... 33 asynchronous interface ......................................................................................................... .................................................... 35 synchronous interface .......................................................................................................... ..................................................... 36 biu summation .................................................................................................................. ........................................................ 36 biu implementation principles .................................................................................................. ................................................. 37 queue management unit (qmu).................................................................................................... .............................. 38 transmit queue (txq) frame format .............................................................................................. ......................................... 38
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 5 m9999-102207-1.6 receive queue (rxq) frame format............................................................................................... ......................................... 39 eeprom interface ............................................................................................................... ........................................ 40 loopback support ............................................................................................................... ......................................... 42 near-end (remote) loopback..................................................................................................... ............................................... 42 cpu interface i/o registers .................................................................................................... ........................................... 43 i/o registers .................................................................................................................. ............................................................ 43 internal i/o space mapping ..................................................................................................... .................................................. 44 register map: mac and phy ...................................................................................................... ....................................... 52 bit type definition ............................................................................................................ ............................................ 52 bank 0-63 bank select register (0x0e) : bsr (same location in all banks) ........................................................ ........ 52 bank 0 base address register (0x00): bar....................................................................................... ......................... 52 bank 0 qmu rx flow control high watermark configuration register (0x04): qrfcr ........................................... 53 bank 0 bus error status register (0x06): besr .................................................................................. ....................... 53 bank 0 bus burst length register (0x08): bblr.................................................................................. ....................... 53 bank 1: reserved ............................................................................................................... .......................................... 53 bank 2 host mac address register low (0x00): marl .............................................................................. ............... 54 bank 2 host mac address register middle (0x02): marm ........................................................................... ............. 54 bank 2 host mac address register high (0x04): marh............................................................................. ............... 54 bank 3 on-chip bus control register (0x00): obcr ............................................................................... ................... 55 bank 3 eeprom control register (0x02): eepcr ................................................................................... .................. 55 bank 3 memory bist info register (0x04): mbir.................................................................................. ...................... 56 bank 3 global reset register (0x06): grr....................................................................................... .......................... 56 bank 3 power management capabilities register (0x08): pmcr ..................................................................... .......... 56 bank 3 wakeup frame contro l register (0x0a): wfcr .............................................................................. ............... 57 bank 4 wakeup frame 0 crc0 register (0x00): wf0crc0............................................................................ .......... 58 bank 4 wakeup frame 0 crc1 register (0x02): wf0crc1............................................................................ .......... 58 bank 4 wakeup frame 0 byte mask 0 register (0x04): wf0bm0 ...................................................................... ........ 58 bank 4 wakeup frame 0 byte mask 1 register (0x06): wf0bm1 ...................................................................... ........ 58 bank 4 wakeup frame 0 byte mask 2 register (0x08): wf0bm2 ...................................................................... ........ 58 bank 4 wakeup frame 0 byte mask 3 register (0 x0a): wf0bm3...................................................................... ........ 59 bank 5 wakeup frame 1 crc0 register (0x00): wf1crc0............................................................................ .......... 59 bank 5 wakeup frame 1 crc1 register (0x02): wf1crc1............................................................................ .......... 59 bank 5 wakeup frame 1 byte mask 0 register (0x04): wf1bm0 ...................................................................... ........ 59 bank 5 wakeup frame 1 byte mask 1 register (0x06): wf1bm1 ...................................................................... ........ 59 bank 5 wakeup frame 1 byte mask 2 register (0x08): wf1bm2 ...................................................................... ........ 60 bank 5 wakeup frame 1 byte mask 3 register (0 x0a): wf1bm3...................................................................... ........ 60 bank 6 wakeup frame 2 crc0 register (0x00): wf2crc0............................................................................ .......... 60 bank 6 wakeup frame 2 crc1 register (0x02): wf2crc1............................................................................ .......... 60 bank 6 wakeup frame 2 byte mask 0 register (0x04): wf2bm0 ...................................................................... ........ 60 bank 6 wakeup frame 2 byte mask 1 register (0x06): wf2bm1 ...................................................................... ........ 61 bank 6 wakeup frame 2 byte mask 2 register (0x08): wf2bm2 ...................................................................... ........ 61 bank 6 wakeup frame 2 byte mask 3 register (0 x0a): wf2bm3...................................................................... ........ 61 bank 7 wakeup frame 3 crc0 register (0x00): wf3crc0............................................................................ .......... 61 bank 7 wakeup frame 3 crc1 register (0x02): wf3crc1............................................................................ .......... 61 bank 7 wakeup frame 3 byte mask 0 register (0x04): wf3bm0 ...................................................................... ........ 62 bank 7 wakeup frame 3 byte mask 1 register (0x06): wf3bm1 ...................................................................... ........ 62 bank 7 wakeup frame 3 byte mask 2 register (0x08): wf3bm2 ...................................................................... ........ 62 bank 7 wakeup frame 3 byte mask 3 register (0 x0a): wf3bm3...................................................................... ........ 62 bank 8 ? 15: reserved .......................................................................................................... ....................................... 62 bank 16 transmit control register (0x00): txcr ................................................................................. ...................... 63 bank 16 transmit status register (0x02): txsr.................................................................................. ....................... 63 bank 16 receive control register (0x04): rxcr.................................................................................. ...................... 64 bank 16 txq memory information register (0x08): txmir.......................................................................... .............. 64
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 6 m9999-102207-1.6 bank 16 rxq memory information register (0x0a): rxmir.......................................................................... ............. 65 bank 17 txq command register (0x00): txqcr ..................................................................................... ................. 65 bank 17 rxq command register (0x02): rxqcr ..................................................................................... ................ 65 bank 17 tx frame data pointer register (0x04): txfdpr .......................................................................... .............. 66 bank 17 rx frame data pointer register (0x06): rxfdpr .......................................................................... ............. 66 bank 17 qmu data register low (0x08): qdrl ..................................................................................... .................... 67 bank 17 qmu data register high (0x0a): qdrh .................................................................................... ................... 67 bank 18 interrupt enable register (0x00): ier .................................................................................. .......................... 68 bank 18 interrupt status register (0x02): isr .................................................................................. ........................... 69 bank 18 receive status register (0x04): rxsr ................................................................................... ...................... 70 bank 18 receive byte count register (0x06): rxbc............................................................................... ................... 70 bank 18 early transmit register (0x08): etxr................................................................................... ........................ 71 bank 18 early receive register (0x0a): erxr .................................................................................... ....................... 71 bank 19 multicast table re gister 0 (0x00): mtr0................................................................................ ....................... 71 bank 19 multicast table re gister 1 (0x02): mtr1................................................................................ ....................... 72 bank 19 multicast table re gister 2 (0x04): mtr2................................................................................ ....................... 72 bank 19 multicast table re gister 3 (0x06): mtr3................................................................................ ....................... 72 bank 19 power management control and status register (0x08): pmcs .............................................................. .... 72 banks 20 ? 31: reserved ........................................................................................................ ..................................... 73 bank 32 chip id and enable register (0x00): cider .............................................................................. ................... 73 bank 32 chip global control register (0x0a): cgcr .............................................................................. ................... 74 banks 33 ? 41: reserved ........................................................................................................ ..................................... 74 bank 42 indirect access control register (0x00): iacr .......................................................................... .................... 75 bank 42 indirect access data register 1 (0x02): iadr1 .......................................................................... ................... 75 bank 42 indirect access data register 2 (0x04): iadr2 .......................................................................... ................... 75 bank 42 indirect access data register 3 (0x06): iadr3 .......................................................................... ................... 75 bank 42 indirect access data register 4 (0x08): iadr4 .......................................................................... ................... 75 bank 42 indirect access data register 5 (0x0a): iadr5 .......................................................................... .................. 75 bank 43? 44: reserved .......................................................................................................... ...................................... 75 bank 45 phy 1 mii-register basic control register (0x00): p1mbcr ............................................................... ........ 76 bank 45 phy 1 mii-register basic status register (0x02): p1mbsr................................................................ ......... 77 bank 45 phy 1 phyid low register (0x04): phy1ilr............................................................................... ................ 77 bank 45 phy 1 phyid high register (0x06): phy1ihr .............................................................................. ............... 78 bank 45 phy 1 auto-negotiation advert isement register (0x08): p1anar........................................................... .... 78 bank 45 phy 1 auto-negotiation link partner ability register (0x0a): p1anlpr ................................................... .. 78 bank 46: reserved .............................................................................................................. ......................................... 79 bank 47 phy1 linkmd contro l/status (0x00): p1vct ............................................................................... ................. 79 bank 47 phy1 special control/stat us register (0x02): p1phyctrl ................................................................. ....... 80 bank 48: reserved .............................................................................................................. ......................................... 80 bank 49 port 1 phy special control/ status, linkmd (0x00): p1scslmd ............................................................. .... 81 bank 49 port 1 control register 4 (0x02): p1cr4................................................................................ ....................... 82 bank 49 port 1 status register (0x04): p1sr .................................................................................... ......................... 83 banks 50 ? 63: reserved ........................................................................................................ ..................................... 84 mib (management inform ation base) counters..................................................................................... .......................... 85 additional mib information ..................................................................................................... ...................................... 86 absolute maximum ratings (1) ............................................................................................................................... ............. 87 operating ratings (1) ............................................................................................................................... ............................. 87 electrical characteristics (1) ............................................................................................................................... ................. 88 timing speci ficati ons .......................................................................................................... ............................................... 89 asynchronous timing without usi ng address strobe (adsn = 0) .................................................................... ........... 89 asynchronous timing using address strobe (adsn) ................................................................................ .................. 90 asynchronous timing using datacsn .............................................................................................. ......................... 91
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 7 m9999-102207-1.6 address latching ti ming for all modes.......................................................................................... ............................................ 92 synchronous timing in burst write (vlbusn = 1) ................................................................................. ................................... 93 synchronous timing in burst read (vlbusn = 1) .................................................................................. .................................. 94 synchronous write timing (vlbusn = 0) .......................................................................................... ....................................... 95 synchronous read timing (vlbusn = 0) ........................................................................................... ...................................... 96 auto negotiation timing........................................................................................................ ..................................................... 97 reset timing................................................................................................................... ........................................................... 98 eeprom timing.................................................................................................................. ...................................................... 99 selection of isolat ion transformers............................................................................................ .................................... 100 selection of re ference crystal ................................................................................................. ....................................... 100 package info rmation ............................................................................................................ ............................................. 101 acronyms a nd glos sary.......................................................................................................... ......................................... 104
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 8 m9999-102207-1.6 list of figures figure 1. ksz8841m functional diagram.......................................................................................... ..................................... 1 figure 2. standard ? ks z8841-16mql 128-pin pqfp ................................................................................ ........................ 10 figure 3. option ? ksz 8841-16mvl 128-pin lqfp.................................................................................. ........................... 10 figure 4. ksz8841-16mbl 100- ball lfbga (top view).............................................................................. ........................ 11 figure 5. standard ? ks z8841-32mql 128-pin pqfp ................................................................................ ........................ 21 figure 6. option ? ksz 8841-32mvl 128-pin lqfp.................................................................................. ........................... 21 figure 7. typical stra ight cable connection .................................................................................... .................................... 30 figure 8. typical crossover cable connection ................................................................................... ................................. 30 figure 9. auto negotiati on and parallel operation .............................................................................. ................................. 31 figure 10. mapping from the isa, eisa, and vlbus to the ksz8841m bus interface................................................. ........ 37 figure 11. ksz8841m 8-bit, 16-bi t, and 32-bit data bus connections............................................................. ................... 37 figure 12. phy port 1 near -end (remote) loopback path.......................................................................... ........................ 42 figure 13. asynchronous cycle ? adsn = 0 ....................................................................................... ................................. 89 figure 14. asynchronous cycle ? using adsn..................................................................................... ............................... 90 figure 15. asynchronous cycle ? using datacsn.................................................................................. ........................... 91 figure 16. address latchin g cycle for all modes ................................................................................ ................................. 92 figure 17. synchronous burst wr ite cycles ? vlbusn = 1......................................................................... ........................ 93 figure 18. synchronous burst read cycles ? vlbusn = 1 .......................................................................... ...................... 94 figure 19. synchronous writ e cycle ? vlbusn = 0................................................................................ ............................ 95 figure 20. synchronous read cycle ? vlbusn = 0................................................................................. ........................... 96 figure 21. auto negotiation timing............................................................................................. .......................................... 97 figure 22. reset timing........................................................................................................ ................................................ 98 figure 23. eeprom read cycle timing diagram ................................................................................... ........................... 99 figure 24. 128-pin pqfp package................................................................................................ ..................................... 101 figure 25. optional 128-pin lqfp package....................................................................................... ................................ 102 figure 26. optional 100- ball lfbg a package ..................................................................................... .............................. 103
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 9 m9999-102207-1.6 list of tables table 1. mdi/mdi-x pin definitions ............................................................................................. ......................................... 30 table 2. bus interface unit signal grouping.................................................................................... ..................................... 35 table 3. frame format for transmit queue ....................................................................................... .................................. 38 table 4. transmit control word bit fields ...................................................................................... ...................................... 38 table 5. transmit byte count format............................................................................................ ....................................... 39 table 6. frame format for receive queue ........................................................................................ .................................. 39 table 7. rxq receive packet status word ........................................................................................ ................................. 40 table 8. rxq receive packet byte count word.................................................................................... .............................. 40 table 9. ksz8841m eeprom format ................................................................................................ ................................. 40 table 10. configparam word in eeprom format.................................................................................... ........................... 41 table 11. format of mib counters............................................................................................... ......................................... 85 table 12. port 1 mib counters indirect memory offsets .......................................................................... ............................ 86 table 13. maxi mum ratings ...................................................................................................... ........................................... 87 table 14. operating ratings .................................................................................................... ............................................. 87 table 15. electrical characteristics........................................................................................... ............................................ 88 table 16. asynchronous cycle (adsn = 0) timing parameters ...................................................................... .................... 89 table 17. asynchronous cycle using adsn timing parameters ...................................................................... ................... 90 table 18. asynchronous cycle us ing datacsn timing parameters................................................................... ............... 91 table 19. address latching timing parameters................................................................................... ................................ 92 table 20. synchronous burs t write timing parameters............................................................................ ........................... 93 table 21. synchronous burs t read timing parameters ............................................................................. ......................... 94 table 22. synchronous write (v lbusn = 0) timi ng parameters ..................................................................... ................... 95 table 23. synchronous read (vlb usn = 0) timing parameters...................................................................... .................. 96 table 24. auto negotiat ion timing parameters ................................................................................... ................................. 97 table 25. reset timing parameters .............................................................................................. ....................................... 98 table 26. eeprom timing parameters ............................................................................................ .................................. 99 table 27. transformer selection criteria ....................................................................................... ..................................... 100 table 28. qualified sing le port magnetics ...................................................................................... .................................... 100 table 29. typical reference crystal characteristics ............................................................................ .............................. 100
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 10 m9999-102207-1.6 pin configuration for ksz8841-16 chip (8/16-bit) p1led2 p1led1 p1led0 nc nc nc dgnd vddio rdyrtnn ardy nc vlbusn eesk swr wrn dgnd pwrdn agnd vdda 103 bclk nc pmen srdyn intrn ldevn rdn eecs cyclen dgnd vddco eeen p1led3 eedo eedi aen adsn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vdda iset agnd nc nc nc rxp1 rxm1 agnd txp1 txm1 vddatx vddarx nc nc agnd nc nc vdda agnd agnd nc nc agnd vddap nc a1 a4 a6 a8 a10 a12 a14 a15 rstn x2 vddc dgnd be0n be1n nc a2 a3 a5 vddio dgnd a7 a9 a11 a13 x1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 scanen testen d0 d1 d2 vddio dgnd d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 vddio dgnd 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 64 ksz8841-16 mql agnd (top view) vddio dgnd nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc figure 2. standard ? ksz8841-16mql 128-pin pqfp p1led2 p1led1 p1led0 nc nc nc dgnd vddio rdyrtnn ardy nc vlbusn eesk swr wrn dgnd pwrdn agnd vdda 103 bclk nc pmen srdyn intrn ldevn rdn eecs cyclen dgnd vddco eeen p1led3 eedo eedi aen adsn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vdda iset agnd nc nc nc rxp1 rxm1 agnd txp1 txm1 vddatx vddarx nc nc agnd nc nc vdda agnd agnd nc nc agnd vddap nc nc nc nc nc nc nc nc nc nc a1 a4 a6 a8 a10 a12 a14 a15 rstn x2 nc nc vddc dgnd nc be0n be1n nc a2 a3 a5 vddio dgnd a7 a9 a11 a13 x1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 scanen nc testen d0 d1 d2 vddio dgnd d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 nc vddio dgnd nc nc 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 64 ksz8841-16 mvl agnd (top view) dgnd vddio figure 3. option ? ksz8841-16mvl 128-pin lqfp
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 11 m9999-102207-1.6 ball configuration for ksz8841-16 chip (8/16-bit) figure 4. ksz8841-16mbl 100-ball lfbga (top view)
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 12 m9999-102207-1.6 pin description for ksz8841-16 chip (8/16-bit) pin number pin name type pin function 1 test_en i test enable for normal operation, pull-down this pin-to-ground. 2 scan_en i scan test scan mux enable for normal operation, pull-down this pin-to-ground. 3 p1led2 opu 4 p1led1 opu 5 p1led0 opu port 1 led indicators 1 defined as follows: chip global control register: cgcr bit [15,9] [0,0] default [0,1] p1led3 2 ? ? p1led2 link/act 100link/act p1led1 full duplex/col 10link/act p1led0 speed full duplex reg. cgcr bit [15,9] [1,0] [1,1] p1led3 2 act ? p1led2 link ? p1led1 full duplex/col ? p1led0 speed ? notes: 1. link = on; activity = blink; link/act = on/blink; full dup/col = on/blink; full duplex = on (full duplex); off (half duplex) speed = on (100base-t); off (10base-t) 2. p1led3 is pin 27. 6 nc opu no connect. 7 nc opu no connect. 8 nc opu no connect. 9 dgnd gnd digital ground 10 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 11 rdyrtnn ipd ready return not: for vlbus-like mode: asserted by the host to complete synchronous read cycles. if the host doesn?t connect to this pin, assert this pin. for burst mode (32-bit interface only): host drives this pin low to signal waiting states. 12 bclk ipd bus interface clock local bus clock for synchronous bus systems. maximum frequency is 50mhz. this pin should be tied low or unconnected if it is in asynchronous mode. 13 nc ipu no connect. 14 pmen opu power management event not when asserted (low), this signal indicates that a power management event has occurred in the system when a wake-up signal is detected by ksz8841m.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 13 m9999-102207-1.6 pin number pin name type pin function 15 srdyn opu synchronous ready not ready signal to interface with synchronous bus for both eisa-like and vlbus-like extend accesses. for vlbus-like mode, the falling edge of this signal indicates ready. this signal is synchronous to the bus clock signal bclk. for burst mode (32-bit interface only), the ksz8841m drives this pin low to signal wait states. 16 intrn opd interrupt active low signal to host cpu to indicate an interrupt status bit is set, this pin need an external 4.7k pull-up resistor. 17 ldevn opd local device not active low output signal, asserted when aen is low and a15-a4 decode to the ksz8841m address programmed into the high byte of the base address register. ldevn is a combinational decode of the address and aen signal. 18 rdn ipd read strobe not asynchronous read strobe, active low. 19 eecs opu eeprom chip select this signal is used to select an external eeprom device. 20 ardy opd asynchronous ready ardy may be used when interfacing asynchronous buses to extend bus access cycles. it is asynchronous to the host cpu or bus clock. this pin need an external 4.7k pull-up resistor. 21 cyclen ipd cycle not for vlbus-like mode cycle signal; this pin follows the addressing cycle to signal the command cycle. for burst mode (32-bit interface only), this pin stays high for read cycles and low for write cycles. 22 nc opd no connect 23 dgnd gnd digital io ground 24 vddco p 1.2v digital core voltage output (internal 1.2v ldo power supply output), this 1.2v output pin provides power to vddc, vdda and vddap pins. it is recommended this pin should be connected to 3.3v power rail by a 100 ohm resistor for the internal ldo application note: internally generated power voltage. do not connect an external power supply to this pin. this pin is used for connecting external filter (ferrite bead and capacitors). 25 vlbusn ipd vlbus-like mode pull-down or float: bus interface is configured for synchronous mode. pull-up: bus interface is configured for 8-bi t or 16-bit asynchronous mode or eisa-like burst mode. 26 eeen ipd eeprom enable eeprom is enabled and connected when this pin is pull-up. eeprom is disabled when this pin is pull-down or no connect. 27 p1led3 opd port 1 led indicator see the description in pins 3, 4, and 5. 28 eedo opd eeprom data out this pin is connected to di input of the serial eeprom. 29 eesk opd eeprom serial clock a 4 s (obcr[1:0]=11 on-chip bus speed @ 25 mhz) or 800 ns (obcr[1:0]=00 on-chip bus speed @ 125 mhz) serial output clock cycle to load configuration data from the serial eeprom.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 14 m9999-102207-1.6 pin number pin name type pin function 30 eedi ipd eeprom data in this pin is connected to do output of the serial eeprom when eeen is pull-up. this pin can be pull-down for 8-bit bus mode, pull-up for 16-bus mode or don?t care for 32- bus mode when eeen is pull-down (without eeprom). 31 swr ipd synchronous write/read write/read signal for synchronous bus accesses. write cycles when high and read cycles when low. 32 aen ipu address enable address qualifier for the address decoding, active low. 33 wrn ipd write strobe not asynchronous write strobe, active low. 34 dgnd gnd digital io ground 35 adsn ipd address strobe not for systems that require address latching, the rising edge of adsn indicates the latching moment of a15-a1 and aen. 36 pwrdn ipu full-chip power-down. active low (low = power down; high or floating = normal operation). 37 agnd gnd analog ground 38 vdda p 1.2v analog v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 39 agnd gnd analog ground 40 nc ? no connect 41 nc ? no connect 42 agnd gnd analog ground 43 vdda p 1.2v analog v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 44 nc ? no connect 45 rxp1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (+ differential) 46 rxm1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (? differential) 47 agnd gnd analog ground 48 txp1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (+ differential) 49 txm1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (? differential) 50 vddatx p 3.3v analog v dd input power supply with well decoupling capacitors. 51 vddarx p 3.3v analog v dd input power supply with well decoupling capacitors. 52 nc ? no connect 53 nc ? no connect 54 agnd gnd analog ground 55 nc ? no connect 56 nc ? no connect 57 vdda p 1.2 analog v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 58 agnd gnd analog ground 59 nc ipu no connect 60 nc ipu no connect 61 iset o set physical transmits output current. pull-down this pin with a 3.01k 1% resistor to ground. 62 agnd gnd analog ground
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 15 m9999-102207-1.6 pin number pin name type pin function 63 vddap p 1.2v analog v dd for pll input power supply from vddco (pin24) through external ferrite bead and capacitor. 64 agnd gnd analog ground 65 x1 i 66 x2 o 25mhz crystal or oscillator clock connection. pins (x1, x2) connect to a crystal. if an oscillator is used, x1 connects to a 3.3v tolerant oscillator and x2 is a no connect. note: clock requirement is 50ppm for either crystal or oscillator. 67 rstn ipu reset not hardware reset pin (active low). this reset input is required minimum of 10ms low after stable supply voltage 3.3v. 68 a15 i address 15 69 a14 i address 14 70 a13 i address 13 71 a12 i address 12 72 a11 i address 11 73 a10 i address 10 74 a9 i address 9 75 a8 i address 8 76 a7 i address 7 77 a6 i address 6 78 dgnd gnd digital io ground 79 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 80 a5 i address 5 81 a4 i address 4 82 a3 i address 3 83 a2 i address 2 84 a1 i address 1 85 nc i no connect 86 nc i no connect 87 be1n i byte enable 1 not, active low for data byte 1 enable (don?t care in 8-bit bus mode). 88 be0n i byte enable 0 not, active low for data byte 0 enable (there is an internal inverter enabled and connected to the be1n for 8-bit bus mode). 89 nc i no connect 90 dgnd gnd digital core ground 91 vddc p 1.2v digital core v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 92 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 93 nc i no connect 94 nc i no connect 95 nc i no connect 96 nc i no connect 97 nc i no connect 98 nc i no connect 99 nc i no connect 100 nc i no connect 101 nc i no connect 102 nc i no connect
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 16 m9999-102207-1.6 pin number pin name type pin function 103 nc i no connect 104 nc i no connect 105 nc i no connect 106 nc i no connect 107 dgnd gnd digital io ground 108 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 109 nc i no connect 110 d15 i/o data 15 111 d14 i/o data 14 112 d13 i/o data 13 113 d12 i/o data 12 114 d11 i/o data 11 115 d10 i/o data 10 116 d9 i/o data 9 117 d8 i/o data 8 118 d7 i/o data 7 119 d6 i/o data 6 120 d5 i/o data 5 121 d4 i/o data 4 122 d3 i/o data 3 123 dgnd gnd digital io ground 124 dgnd gnd digital core ground 125 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 126 d2 i/o data 2 127 d1 i/o data 1 128 d0 i/o data 0 legend: p = power supply gnd = ground i/o = bi-directional i = input o = output. ipd = input with internal pull-down. ipu = input with internal pull-up. opd = output with internal pull-down. opu = output with internal pull-up.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 17 m9999-102207-1.6 ball description for ksz8841-16 chip (8/16-bit) ball number ball name type ball function e8 test_en i test enable for normal operation, pull-down this ball to ground. d10 scan_en i scan test scan mux enable for normal operation, pull-down this ball to ground. a10 p1led2 opu b10 p1led1 opu c10 p1led0 opu port 1 led indicators 1 defined as follows: switch global control register 5: sgcr5 bit [15,9] [0,0] default [0,1] p1led3 2 ? ? p1led2 link/act 100link/act p1led1 full duplex/col 10link/act p1led0 speed full duplex reg. sgcr5 bit [15,9] [1,0] [1,1] p1led3 2 act ? p1led2 link ? p1led1 full duplex/col ? p1led0 speed ? notes: 1. link = on; activity = blink; link/act = on/blink; full dup/col = on/blink; full duplex = on (full duplex); off (half duplex) speed = on (100base-t); off (10base-t) 2. p1led3 is ball a4. d9 rdyrtnn ipd ready return not: for vlbus-like mode: asserted by the host to complete synchronous read cycles. if the host doesn?t connect to this ball, assert this ball. a8 bclk ipd bus interface clock local bus clock for synchronous bus systems. maximum frequency is 50mhz. this ball should be tied low or unconnected if it is in asynchronous mode. d8 pmen opu power management event not when asserted (low), this signal indicates that a power management event has occurred in the system when a wake-up signal is detected by ksz8841m. b8 srdyn opu synchronous ready not ready signal to interface with synchronous bus for both eisa-like and vlbus- like extend accesses. for vlbus-like mode, the falling edge of this signal indicates ready. this signal is synchronous to the bus clock signal bclk. c8 intrn opd interrupt active low signal to host cpu to indicate an interrupt status bit is set, this ball need an external 4.7k pull-up resistor. a7 ldevn opd local device not
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 18 m9999-102207-1.6 ball number ball name type ball function active low output signal, asserted when aen is low and a15-a4 decode to the ksz8841m address programmed into the high byte of the base address register. ldevn is a combinational decode of the address and aen signal. b7 rdn ipd read strobe not asynchronous read strobe, active low. c7 eecs opu eeprom chip select a6 ardy opd asynchronous ready ardy may be used when interfacing asynchronous buses to extend bus access cycles. it is asynchronous to the host cpu or bus clock. this ball needs an external 4.7k pull-up resistor. b6 cyclen ipd cycle not for vlbus-like mode cycle signal; this ball follows the addressing cycle to signal the command cycle. for burst mode (32-bit interface only), this ball stays high for read cycles and low for write cycles. a5 vlbusn ipd vlbus-like mode pull-down or float: bus interface is configured for synchronous mode. pull-up: bus interface is configured for 8-bit or 16-bit asynchronous mode or eisa-like burst mode. b5 eeen ipd eeprom enable eeprom is enabled and connected when this ball is pull-up. eeprom is disabled when this ball is pull-down or no connect. a4 p1led3 opd port 1 led indicator see the description in balls a10, b10, and c10. b4 eedo opd eeprom data out this ball is connected to di input of the serial eeprom. a3 eesk opd eeprom serial clock a 4 s (obcr[1:0]=11 on-chip bus speed @ 25 mhz) or 800 ns (obcr[1:0]=00 on-chip bus speed @ 125 mhz) serial output clock cycle to load configuration data from the serial eeprom. b3 eedi ipd eeprom data in this ball is connected to do output of the serial eeprom when eeen is pull- up. this ball can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or don?t care for 32-bit bus mode when eeen is pull-down (without eeprom). c3 swr ipd synchronous write/read write/read signal for synchronous bus accesses. write cycles when high and read cycles when low. a2 aen ipu address enable address qualifier for the address decoding, active low. b2 wrn ipd write strobe not asynchronous write strobe, active low. a1 adsn ipd address strobe not for systems that require address latching, the rising edge of adsn indicates the latching moment of a15-a1 and aen. b1 pwrdn ipu full-chip power-down. low = power down; high or floating = normal operation.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 19 m9999-102207-1.6 ball number ball name type ball function c1 rxp1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (+ differential) c2 rxm1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (? differential) d1 txp1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (+ differential) d2 txm1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (? differential) h2 test2 ipu test input 2 for normal operation, left this ball open. g3 iset o set physical transmits output current. pull-down this ball with a 3.01k 1% resistor to ground. j1 x1 i k1 x2 o 25mhz crystal or oscillator clock connection. balls (x1, x2) connect to a crystal. if an oscillator is used, x1 connects to a 3.3v tolerant oscillator and x2 is a no connect. note: clock requirement is 50ppm for either crystal or oscillator. j2 rstn ipu hardware reset ball (active low). this reset input is required minimum of 10ms low after stable supply voltage 3.3v. k2 a15 i address 15 k3 a14 i address 14 j3 a13 i address 13 h3 a12 i address 12 k4 a11 i address 11 j4 a10 i address 10 h4 a9 i address 9 k5 a8 i address 8 j5 a7 i address 7 h5 a6 i address 6 k6 a5 i address 5 j6 a4 i address 4 h6 a3 i address 3 k7 a2 i address 2 j7 a1 i address 1 h7 be1n i byte enable 1 not, active low for data byte 1 enable (don?t care in 8-bit bus mode). k8 be0n i byte enable 0 not, active low for data byte 0 enable (there is an internal inverter enabled and connected to the be1n for 8-bit bus mode). k9 d15 i/o data 15 k10 d14 i/o data 14 j9 d13 i/o data 13 j10 d12 i/o data 12 j8 d11 i/o data 11 h9 d10 i/o data 10 h10 d9 i/o data 9 h8 d8 i/o data 8 g9 d7 i/o data 7 g10 d6 i/o data 6 g8 d5 i/o data 5 f9 d4 i/o data 4 f10 d3 i/o data 3
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 20 m9999-102207-1.6 ball number ball name type ball function f8 d2 i/o data 2 e9 d1 i/o data 1 e10 d0 i/o data 0 c4 vddco p 1.2v digital core voltage output (internal 1.2v ldo power supply output), this 1.2v output ball provides power to all vddc/vdda balls. it is recommended this ball should be connected to 3.3v power rail by a 100 ohm resistor for the internal ldo application. note: internally generated power voltage. do not connect an external power supply to this ball. this ball is used for connecting external filter (ferrite bead and capacitors). c5 vddc p 1.2v digital core v dd input power supply from vddco (ball c4) through external ferrite bead and capacitor. d3, e3, f3 vdda p 1.2v analog v dd input power supply from vddco (ball c4) through external ferrite bead and capacitor. e1 vddatx p 3.3v analog v dd input power supply with well decoupling capacitors. e2 vddarx p 3.3v analog v dd input power supply with well decoupling capacitors. d7, e7, f7, g4, g5, g6, g7 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. d4, d5, d6, e4, e5, e6, f4, f5, f6 gnd gnd all digital and analog grounds h1, a9, b9, c9, c6, f2, f1, g2, g1 nc i/o no connect
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 21 m9999-102207-1.6 pin configuration for ksz8841-32 chip (32-bit) p1led2 p1led1 p1led0 nc nc nc dgnd vddio rdyrtnn ardy nc vlbusn eesk swr wrn dgnd pwrdn agnd vdda 103 bclk datacsn pmen srdyn intrn ldevn rdn eecs cyclen dgnd vddco eeen p1led3 eedo eedi aen adsn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vdda iset agnd nc nc nc rxp1 rxm1 agnd txp1 txm1 vddatx vddarx nc nc agnd nc nc vdda agnd agnd nc nc agnd vddap d21 d22 d23 d24 d25 d26 d28 d27 be2n a1 a4 a6 a8 a10 a12 a14 a15 rstn x2 d29 d30 vddc dgnd d31 be0n be1n be3n a2 a3 a5 vddio dgnd a7 a9 a11 a13 x1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 scanen d17 testen d0 d1 d2 vddio dgnd d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 vddio dgnd d18 d19 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 64 ksz8841-32 mql agnd (top view) vddio dgnd d20 figure 5. standard ? ksz8841-32mql 128-pin pqfp p1led2 p1led1 p1led0 nc nc nc dgnd vddio rdyrtnn ardy nc vlbusn eesk swr wrn dgnd pwrdn agnd vdda 103 bclk datacsn pmen srdyn intrn ldevn rdn eecs cyclen dgnd vddco eeen p1led3 eedo eedi aen adsn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vdda iset agnd nc nc nc rxp1 rxm1 agnd txp1 txm1 vddatx vddarx nc nc agnd nc nc vdda agnd agnd nc nc agnd vddap d20 d21 d22 d23 d24 d25 d26 d28 d27 be2n a1 a4 a6 a8 a10 a12 a14 a15 rstn x2 d29 d30 vddc dgnd d31 be0n be1n be3n a2 a3 a5 vddio dgnd a7 a9 a11 a13 x1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 scanen d17 testen d0 d1 d2 vddio dgnd d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 vddio dgnd d18 d19 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 64 ksz8841-32 mvl agnd (top view) dgnd vddio figure 6. option ? ksz8841-32mvl 128-pin lqfp
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 22 m9999-102207-1.6 pin description for ksz8841-32 chip (32-bit) pin number pin name type pin function 1 test_en i test enable for normal operation, pull-down this pin-to-ground. 2 scan_en i scan test scan mux enable for normal operation, pull-down this pin-to-ground. 3 p1led2 opu 4 p1led1 opu 5 p1led0 opu port 1 led indicators 1 defined as follows: chip global control register: cgcr bit [15,9] [0,0] default [0,1] p1led3 2 ? ? p1led2 link/act 100link/act p1led1 full duplex/col 10link/act p1led0 speed full duplex reg. cgcr bit [15,9] [1,0] [1,1] p1led3 2 act ? p1led2 link ? p1led1 full duplex/col ? p1led0 speed ? notes: 1. link = on; activity = blink; link/act = on/blink; full dup/col = on/blink; full duplex = on (full duplex); off (half duplex) speed = on (100base-t); off (10base-t) 2. p1led3 is pin 27. 6 nc opu no connect. 7 nc opu no connect. 8 nc opu no connect. 9 dgnd gnd digital ground 10 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 11 rdyrtnn ipd ready return not: for vlbus-like mode: asserted by the host to complete synchronous read cycles. if the host doesn?t connect to this pin, assert this pin. for burst mode (32-bit interface only): host drives this pin low to signal waiting states. 12 bclk ipd bus interface clock local bus clock for synchronous bus systems. maximum frequency is 50mhz. this pin should be tied low or unconnected if it is in asynchronous mode. 13 datacsn ipu data chip select not (for ksz8841-32 mode only) chip select signal for qmu data register (qdrh, qdrl), active low. when datacsn is low, the data path can be accessed regardless of the value of aen, a15-a1, and the content of the bank select register. 14 pmen opu power management event not when asserted (low), this signal indicates that a power management event has occurred in the system when a wake-up signal is detected by ksz8841m.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 23 m9999-102207-1.6 pin number pin name type pin function 15 srdyn opu synchronous ready not ready signal to interface with synchronous bus for both eisa-like and vlbus-like extend accesses. for vlbus-like mode, the falling edge of this signal indicates ready. this signal is synchronous to the bus clock signal bclk. for burst mode (32-bit interface only), the ksz8841m drives this pin low to signal wait states. 16 intrn opd interrupt active low signal to host cpu to indicate an interrupt status bit is set, this pin need an external 4.7k pull-up resistor 17 ldevn opd local device not active low output signal, asserted when aen is low and a15-a4 decode to the ksz8841m address programmed into the high byte of the base address register. ldevn is a combinational decode of the address and aen signal. 18 rdn ipd read strobe not asynchronous read strobe, active low. 19 eecs opu eeprom chip select this signal is used to select an external eeprom device. 20 ardy opd asynchronous ready ardy may be used when interfacing asynchronous buses to extend bus access cycles. it is asynchronous to the host cpu or bus clock. this pin need an external 4.7k pull-up resistor. 21 cyclen ipd cycle not for vlbus-like mode cycle signal; this pin follows the addressing cycle to signal the command cycle. for burst mode (32-bit interface only), this pin stays high for read cycles and low for write cycles. 22 nc opd no connect 23 dgnd gnd digital io ground 24 vddco p 1.2v digital core voltage output (internal 1.2v ldo power supply output), this 1.2v output pin provides power to vddc, vdda and vddap pins. it is recommended this ball should be connected to 3.3v power rail by a 100 ohm resistor for the internal ldo application. note: internally generated power voltage. do not connect an external power supply to this pin. this pin is used for connecting external filter (ferrite bead and capacitors). 25 vlbusn ipd vlbus-like mode pull-down or float: bus interface is configured for synchronous mode. pull-up: bus interface is configured for 32-bit asynchronous mode or eisa-like burst mode. 26 eeen ipd eeprom enable eeprom is enabled and connected when this pin is pull-up. eeprom is disabled when this pin is pull-down or no connect. 27 p1led3 opd port 1 led indicator see the description in pins 3, 4, and 5. 28 eedo opd eeprom data out this pin is connected to di input of the serial eeprom. 29 eesk opd eeprom serial clock a 4 s (obcr[1:0]=11 on-chip bus speed @ 25 mhz) or 800 ns (obcr[1:0]=00 on-chip bus speed @ 125 mhz) serial output clock cycle to load configuration data from the serial eeprom.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 24 m9999-102207-1.6 pin number pin name type pin function 30 eedi ipd eeprom data in this pin is connected to do output of the serial eeprom when eeen is pull-up. this pin can be pull-down for 8-bit bus mode, pull-up for 16-bus mode or don?t care for 32- bus mode when eeen is pull-down (without eeprom). 31 swr ipd synchronous write/read write/read signal for synchronous bus accesses. write cycles when high and read cycles when low. 32 aen ipu address enable address qualifier for the address decoding, active low. 33 wrn ipd write strobe not asynchronous write strobe, active low. 34 dgnd gnd digital io ground 35 adsn ipd address strobe not for systems that require address latching, the rising edge of adsn indicates the latching moment of a15-a1 and aen. 36 pwrdn ipu full-chip power-down. active low (low = power down; high or floating = normal operation). 37 agnd gnd analog ground 38 vdda p 1.2v analog v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 39 agnd gnd analog ground 40 nc ? no connect 41 nc ? no connect 42 agnd gnd analog ground 43 vdda p 1.2v analog v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 44 nc ? no connect 45 rxp1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (+ differential) 46 rxm1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (? differential) 47 agnd gnd analog ground 48 txp1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (+ differential) 49 txm1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (? differential) 50 vddatx p 3.3v analog v dd input power supply with well decoupling capacitors. 51 vddarx p 3.3v analog v dd input power supply with well decoupling capacitors. 52 nc ? no connect 53 nc ? no connect 54 agnd gnd analog ground 55 nc ? no connect 56 nc ? no connect 57 vdda p 1.2 analog v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 58 agnd gnd analog ground 59 nc ipu no connect 60 nc ipu no connect 61 iset o set physical transmits output current. pull-down this pin with a 3.01k 1% resistor to ground. 62 agnd gnd analog ground
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 25 m9999-102207-1.6 pin number pin name type pin function 63 vddap p 1.2v analog v dd for pll input power supply from vddco (pin24) through external ferrite bead and capacitor. 64 agnd gnd analog ground 65 x1 i 66 x2 o 25mhz crystal or oscillator clock connection. pins (x1, x2) connect to a crystal. if an oscillator is used, x1 connects to a 3.3v tolerant oscillator and x2 is a no connect. note: clock requirement is 50ppm for either crystal or oscillator. 67 rstn ipu reset not hardware reset pin (active low). this reset input is required minimum of 10ms low after stable supply voltage 3.3v. 68 a15 i address 15 69 a14 i address 14 70 a13 i address 13 71 a12 i address 12 72 a11 i address 11 73 a10 i address 10 74 a9 i address 9 75 a8 i address 8 76 a7 i address 7 77 a6 i address 6 78 dgnd gnd digital io ground 79 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 80 a5 i address 5 81 a4 i address 4 82 a3 i address 3 83 a2 i address 2 84 a1 i address 1 85 be3n i byte enable 3 not, active low for data byte 3 enable 86 be2n i byte enable 2 not, active low for data byte 2 enable 87 be1n i byte enable 1 not, active low for data byte 1 enable 88 be0n i byte enable 0 not, active low for data byte 0 enable 89 d31 i/o data 31 90 dgnd gnd digital core ground 91 vddc p 1.2v digital core v dd input power supply from vddco (pin24) through external ferrite bead and capacitor. 92 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 93 d30 i/o data 30 94 d29 i/o data 29 95 d28 i/o data 28 96 d27 i/o data 27 97 d26 i/o data 26 98 d25 i/o data 25 99 d24 i/o data 24 100 d23 i/o data 23 101 d22 i/o data 22 102 d21 i/o data 21
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 26 m9999-102207-1.6 pin number pin name type pin function 103 d20 i/o data 20 104 d19 i/o data 19 105 d18 i/o data 18 106 d17 i/o data 17 107 dgnd gnd digital io ground 108 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 109 d16 i/o data 16 110 d15 i/o data 15 111 d14 i/o data 14 112 d13 i/o data 13 113 d12 i/o data 12 114 d11 i/o data 11 115 d10 i/o data 10 116 d9 i/o data 9 117 d8 i/o data 8 118 d7 i/o data 7 119 d6 i/o data 6 120 d5 i/o data 5 121 d4 i/o data 4 122 d3 i/o data 3 123 dgnd gnd digital io ground 124 dgnd gnd digital core ground 125 vddio p 3.3v digital v ddio input power supply for io with well decoupling capacitors. 126 d2 i/o data 2 127 d1 i/o data 1 128 d0 i/o data 0 legend: p = power supply gnd = ground i/o = bi-directional i = input o = output. ipd = input with internal pull-down. ipu = input with internal pull-up. opd = output with internal pull-down. opu = output with internal pull-up.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 27 m9999-102207-1.6 functional description the ksz8841m is a single-chip fast ethernet mac controller consisting of a 10/100 physical layer transceiver (phy), a mac, and a bus interface unit (biu) that controls the ksz8841m via an 8-bit, 16-bit, or 32-bit host bus interface. the ksz8841m is fully compliant to ieee802.3u standards. functional overview power management power down the ksz8841m features a port power-down mode. to save power, the user can power-down the port that is not in use by setting bit 11 in either p1cr4 or p1mbcr register for this port. to bring the port back up, reset bit 11 in these registers. in addition, there is a full chip power-down mode pwrdn (pin 36). when this pin is pulled-down, the entire chip powers down. transitioning this pin from pull-down to pull-up results in a power up and chip reset. wake-on-lan wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the network. examples of meaningful data include the reception of a magic packet, a management request from a remote administrator, or simply network traffic directly targeted to the local system. in all of these instances, the network device i s pre-programmed by the policy owner or other software with information on how to identify wake frames from other network traffic. a wake-up event is a request for hardware and/or software external to the network device to put the system into a powered state (working). a wake-up signal is caused by: 1. detection of a change in the network link state 2. receipt of a network wake-up frame 3. receipt of a magic packet there are also other types of wake-up events that are not listed here as manufacturers may choose to implement these in their own way. link change link status wake events are useful to indicate a change in the network?s availability, especially when this change may impact the level at which the system should re-enter the sleeping state. for example, a change from link off to link on may trigger the system to re-enter sleep at a higher level (d2 versus d3 1 ) so that wake frames can be detected. conversely, a transition from link on to link off may trigger the system to re-enter sleep at a deeper level (d3 versus d2) since the network is not currently available. wake-up packet wake-up packets are certain types of packets with specific crc values that a system recognizes as a ?wake up? frame. the ksz8841m supports up to four users defined wake-up frames as below: 1. wake-up frame 0 is defined in registers 0x00-0x0a of bank 4 and is enabled by bit 0 in wakeup frame control register. 2. wake-up frame 1 is defined in registers 0x00-0x0a of bank 5 and is enabled by bit 1 in wakeup frame control register. 3. wake-up frame 2 is defined in registers 0x00-0x0a of bank 6 and is enabled by bit 2 in wakeup frame control register. 4. wake-up frame 4 is defined in registers 0x00-0x0a of bank 7 and is enabled by bit 3 in wakeup frame control register. magic packet magic packet technology is used to remotely wake up a sleeping or powered off pc on a lan. this is accomplished by sending a specific packet of information, called a magic packet frame, to a node on the network. when a pc capable of receiving the specific frame goes to sleep, it enables the magic packet rx mode in the lan controller, and when the lan controller receives a magic packet frame, it will alert the system to wake up. 1 references to d0, d1, d2, and d3 are power management states defined in a similar fashion to the way they are defined for pci. for more information, refer to the pci specification at www.pcisig.com/specifications/conventional/pcipm1.2.pdf.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 28 m9999-102207-1.6 magic packet is a standard feature integrated into the ksz8841m. the controller implements multiple advanced power- down modes including magic packet to conserve power and operate more efficiently. once the ksz8841m has been put into magic packet enable mode (wfcr[7]=1), it scans all incoming frames addressed to the node for a specific data sequence, which indicates to the controller this is a magic packet (mp) frame. a magic packet frame must also meet the basic requirements for the lan technology chosen, such as source address (sa), destination address (da), which may be the receiving station?s ieee address or a multicast or broadcast address and crc. the specific sequence consists of 16 duplications of the ieee address of this node, with no breaks or interruptions. this sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. the synchronization stream allows the scanning state machine to be much simpler. the synchronization stream is defined as 6 bytes of ffh. the device will also accept a broadcast frame, as long as the 16 duplications of the ieee address match the address of the machine to be awakened. example if the ieee address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the lan controller would be scanning for the data sequence (assuming an ethernet frame): destination source ? misc - ff ff ff ff ff ff - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - misc - crc. there are no further restrictions on a magic packet frame. for instance, the sequence could be in a tcp/ip packet or an ipx packet. the frame may be bridged or routed across the network without affecting its ability to wake-up a node at the frame?s destination. if the lan controller scans a frame and does not find the specific sequence shown above, it discards the frame and takes no further action. if the ksz8841m controller detects the data sequence, however, it then alerts the pc?s power management circuitry (assert the pmen pin) to wake up the system. physical layer transceiver (phy) 100base-tx transmit the 100base-tx transmit function performs parallel-to-serial conversion, 4b/5b coding, scrambling, nrz-to-nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel-to-serial conversion, whic h converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding, followed by a scrambler. the serialized data is further converted from nrz-to-nrzi format, and then transmitted in mlt3 current output. an external 1% 3.01k ? resistor for the 1:1 transformer ratio sets the output current. the output signal has a typical rise/fall time of 4ns and complies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave-shaped 10base-t output driver is also incorporated into the 100base-tx driver.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 29 m9999-102207-1.6 100base-tx receive the 100base-tx receiver function performs adaptive equalization, dc restoration, mlt3-to-nrzi conversion, data and clock recovery, nrzi-to-nrz conversion, de-scrambling, 4b/5b decoding, and serial-to-parallel conversion. the receiving side starts with the equalization filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its characteristics to optimize performance. in this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. this is an ongoing process and self-adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc restoration and data conversion block. the dc restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this signal is sent through the de-scrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to an mii format and provided as the input data to the mac. pll clock synthesizer (recovery) the internal pll clock synthesizer generates 125mhz, 62.5mhz, 41.66mhz, and 25mhz clocks by setting the on-chip bus speed control register for ksz8841m system timing. these internal clocks are generated from an external 25mhz crystal or oscillator. scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (emi) and baseline wander. transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (lfsr). the scrambler generates a 2047-bit non-repetitive sequence. then the receiver de-scrambles the incoming data stream using the same sequence as at the transmitter. 10base-t transmit the 10base-t driver is incorporated with the 100base-tx driver to allow for transmission using the same magnetics. they are internally wave-shaped and pre-emphasized into outputs with a typical 2.4v amplitude. the harmonic contents are at least 27db below the fundamental frequency when driven by an all-ones manchester-encoded signal. 10base-t receive on the receive side, input buffers and level detecting squelch circuits are employed. a differential input receiver circuit and a phase-locked loop (pll) perform the decoding function. the manchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv or with short pulse widths to prevent noise at the rxp-or-rxm input from falsely triggering the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ksz8841m decodes a data frame. the receiver clock is maintained active during idle periods in between data reception. mdi/mdi-x auto crossover to eliminate the need for crossover cables between similar devices, the ksz8841m supports hp-auto mdi/mdi-x and ieee 802.3u standard mdi/mdi-x auto crossover. hp-auto mdi/mdi-x is the default. the auto-sense function detects remote transmit and receive pairs and correctly assigns the transmit and receive pairs for the ksz8841m device. this feature is extremely useful when end users are unaware of cable types in addition to saving on an additional uplink configuration connection. the auto-crossover feature can be disabled through the port control registers.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 30 m9999-102207-1.6 the ieee 802.3u standard mdi and mdi-x definitions are: mdi mdi-x rj45 pins signals rj45 pins signals 1 td+ 1 rd+ 2 td- 2 rd- 3 rd+ 3 td+ 6 rd- 6 td- table 1. mdi/mdi-x pin definitions straight cable a straight cable connects an mdi device to an mdi-x device or an mdi-x device to an mdi device. the following diagram shows a typical straight cable connection between a network interface card (nic) and a chip (mdi), or hub (mdi-x). r e c e i v e p a i r t r a n s m i t p a i r r e c e i v e p a i r 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 t r a n s m i t p a i r ( r j - 4 5 ) n i c s t r a i g h t c a b l e 1 0 / 1 0 0 e t h e r n e t m e d i a d e p e n d e n t i n t e r f a c e 1 0 / 1 0 0 e t h e r n e t m e d i a d e p e n d e n t i n t e r f a c e m o d u l a r c o n n e c t o r ( r j - 4 5 ) h u b ( r e p e a t e r o r s w i t c h ) m o d u l a r c o n n e c t o r figure 7. typical straight cable connection crossover cable a crossover cable connects an mdi device to another mdi device, or an mdi-x device to another mdi-x device. the following diagram shows a typical crossover cable connection between two chips or hubs (two mdi-x devices). receive pair receive pair transmi t pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) modular connector (rj-45) hub (repeater or switch) crossover cable figure 8. typical crossover cable connection
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 31 m9999-102207-1.6 auto negotiation the ksz8841m conforms to the auto negotiation protocol as described by the 802.3 committee to allow the port to operate at either 10base-t or 100base-tx. auto negotiation allows unshielded twisted pair (utp) link partners to select the best common mode of operation. in auto negotiation, the link partners advertise capabilities across the link to each other. if auto negotiation is not supported or th e link partner to the ksz8841m is forced to bypass auto negotiation, the mode is set by observing the signal at the receiver. this is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol. the link setup is shown in the following flow diagram (figure 9). force link setting l i s t e n f o r 1 0 base-t l i n k p u l s e s l i s t e n f o r 1 0 0 base-t x idles a ttempt auto negotiation l i n k m o d e s e t b y p a s s a u t o n e g o t i a t i o n and set link mode l i n k m o d e s e t ? parallel operation join flow no no yes yes start auto negotiation figure 9. auto negotiation and parallel operation
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 32 m9999-102207-1.6 linkmd cable diagnostics the ksz8841m linkmd uses time domain reflectometry (tdr) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. linkmd works by sending a pulse of known amplitude and duration down the mdi and mdi-x pairs and then analyzes the shape of the reflected signal. timing the pulse duration gives an indication of the distance to the cabling fault with a maximum distance of 200m and an accuracy of +/?2m. internal circuitry displays the tdr information in a user-readable digital format in register p1vct[8:0]. note: cable diagnostics are only valid for copper connections ? fiber-optic operation is not supported. access linkmd is initiated by accessing register p1vct, the linkmd control/status register, in conjunction with register p1cr4, the 100base-tx phy controller register. usage linkmd can be run at any time by ensuring that auto-mdix has been disabled. to disable auto-mdix, write a ?1? to p1cr4[10] to enable manual control over the pair used to transmit the linkmd pulse. the self-clearing cable diagnostic test enable bit, p1vct[15], is set to ?1? to start the test on this pair. when bit p1vct[15] returns to ?0?, the test is complete. the test result is returned in bits p1vct[14:13] and the distance is returned in bits p1vct[8:0]. the cable diagnostic test results are as follows: 00 = valid test, normal condition 01 = valid test, open circuit in cable 10 = valid test, short circuit in cable 11 = invalid test, linkmd failed if p1vct[14:13]=11, this indicates an invalid test, and occurs when the ksz8841m is unable to shut down the link partner. in this instance, the test is not run, as it is not possible for the ksz8841m to determine if the detected signal is a reflection of the signal generated or a signal from another source. cable distance can be approximated by the following formula: p1vct[8:0] x 0.4m for port 1 cable distance this constant may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm. media access control (mac) operation the ksz8841m strictly abides by ieee 802.3 standards to maximize compatibility. inter packet gap (ipg) if a frame is successfully transmitted, then the minimum 96-bit time for ipg is measured between two consecutive packets. if the current packet is experiencing collisions, the minimum 96-bit time for ipg is measured from carrier sense (crs) to the next transmit packet. back-off algorithm the ksz8841m implements the ieee standard 802.3 binary exponential back-off algorithm in half-duplex mode. after 16 collisions, the packet is dropped. late collision if a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped. flow control the ksz8841m supports standard 802.3x flow control frames on both transmit and receive sides. on the receive side, if the ksz8841m receives a pause control frame, the ksz8841m will not transmit the next normal frame until the timer, specified in the pause control frame, expires. if another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. during this period (while it is flow controlled), only flow control packets from the ksz8841m are transmitted. on the transmit side, the ksz8841m has intelligent and efficient ways to determine when to invoke flow control. the flow
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 33 m9999-102207-1.6 control is based on availability of the system resources. the ksz8841m issues a flow control fram e (xoff, or transmitter of f), containing the maximum pause time defin ed in ieee standard 802.3x. once the resource is freed up, the ksz8841m sends out the another flow control frame (xon, or transmitter on) with zero pause time to turn off the flow control (turn on transmission to the port). a hysteresis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated. half-duplex backpressure a half-duplex backpressure option (non-ieee 802.3 standards) is also provided. the activation and deactivation conditions are the same as in full-duplex mode. if backpressure is required, the ksz8841m sends preambles to defer the other stations' transmission (carrier sense deference). to avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the ksz8841m discontinues the carrier sense and then raises it again quickly. this short silent time (no carrier sense) prevents other stations from sending out packets thus keeping other stations in a carrier sense deferred state. if the port has packets to send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are transmitted instead. if there are no additional packets to send, carrier sense type backpressure is reactivated again until chip resources free up. if a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet reception. clock generator the x1 and x2 pins are connected to a 25mhz crystal. x1 can also serve as the connector to a 3.3v, 25mhz oscillator (as described in the pin description). the bus interface unit (biu) uses bclk (bus clock) for synchronous accesses. the maximum frequency is 50mhz for vlbus-like and eisa-like slave direct memory access (dma). bus interface unit (biu) the biu host interface is a generic bus interface, designed to communicate with embedded processors. the use of glue logic may be required when it talks to various standard buses and processors. supported transfers in terms of transfer type, the biu can support two transfers: asynchronous transfer and synchronous transfer. to support these transfers (asynchronous and synchronous), the biu provides three groups of signals: synchronous signals asynchronous signals common signals are used for both synchronous and asynchronous transfers. since both synchronous and asynchronous signals are independent of each other, synchronous transfer and asynchronous transfer can be mixed or interleaved but cannot be overlapped (due to the sharing of common signals). physical data bus size the biu supports an 8-bit, 16-bit, or 32-bit host standard data bus. depending on the size of the physical data bus, the ksz8841m supports 8-bit, 16-bit, or 32-bit data transfers for example, for a 32-bit system/host data bus, the ksz8841m allows an 8-bit, 16-bit, and 32-bit data transfer (ksz8841-32mql). for a 16-bit system/host data bus, the ksz8841m allows an 8-bit and 16-bit data transfer (ksz8841-16mql). for an 8-bit system/host data bus, the ksz8841m only allows an 8-bit data transfer (ksz8841-16mql). the ksz8841m does not support internal data byte-swap but it does support internal data word-swap. this means that the system/host data bus hd[7:0] must connect to both d[7:0] and d[15:8] for an 8-bit data bus interface. for a 16-bit data bus, the system/host data bus hd[15:8] and hd[7:0] only need to connect to d[15:8] and d[7:0] respectively, and there is no need to connect hd[15:8] and hd[7:0] to d[31:24] and d[23:16]. table 2 describes the biu signal grouping.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 34 m9999-102207-1.6 signal type (1) function common signals a[15:1] i address aen i address enable address enable asserted indicates memory address on the bus for dma access and since the device is an i/o device, address decoding is only enabled when aen is low. be3n, be2n, be1n, be0n i byte enable be0n be1n be2n be3 n description 0 0 0 0 32-bit access 0 0 1 1 lower 16-bit (d[15:0]) access 1 1 0 0 higher 16-bit (d[31:16]) access 0 1 1 1 byte 0 (d[7:0]) access 1 0 1 1 byte 1 (d[15:8]) access 1 1 0 1 byte 2 (d[23:16]) access 1 1 1 0 byte 3 (d[31:24]) access note 1: be3n, be2n, be1n and be0n are ignored when datacsn is low because 32 bit transfers are assumed. note 2: be2n and be3n are valid only for the ksz8841-32 mode, and are no connect for the ksz8841-16 mode. d[31:16] i/o data for ksz8841m-32 mode only. d[15:0] i/o data for both ksz8841-32 and ksz8841-16 modes adsn i address strobe the rising edge of adsn is used to latch a[15:1], aen, be3n, be2n, be1n and be0n. ldevn o local device this signal is a combinatorial decode of aen and a[15:4]. this a[15:4] is used to compare against the base address register. datacsn i data register chip select (for ksz8841-32mql mode only) this signal is used for central decoding architecture (mostly for embedded application). when asserted, the device?s local decoding logic is ignored and the 32- bit access to qmu data register is assumed. intr o interrupt synchronous transfer signals vlbusn i vlbus vlbusn = 0, vlbus-like cycle. vlbusn = 1, burst cycle (both host/system and ksz8841m can insert wait state) cyclen i cyclen for vlbus-like access: used to sample swr when asserted. for burst access: used to connect to iowc# bus signal to indicate burst write. swr i write/read for vlbus-like access: used to indicate write (high) or read (low) transfer. for burst access: used to connect to iorc# bus signal to indicate burst read. srdyn o synchronous ready for vlbus-like access: exactly the same signal definition of nsrdy in vlbus. for burst access: insert wait state by ksz8841m whenever necessary during the data register access. rdyrtnn i ready return for vlbus-like access: exactly like rdyrtnn signal in vlbus to end the cycle.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 35 m9999-102207-1.6 signal type (1) function for burst access: exactly like exrdy signal in eisa to insert wait states. note that the wait states are inserted by system logic (memory) not by ksz8841m. bclk i bus clock asynchronous transfer signals rdn i asynchronous read wrn i asynchronous write ardy o asynchronous ready this signal is asserted (low) to insert wait states. note 1: i = input. o = output. i/o = bi-directional. table 2. bus interface unit signal grouping regardless of whether the transfer is synchronous or asynchronous, if the address latch is required, use the rising edge of adsn to latch the incoming signals a[15:1], aen, be3n, be2n, be1n, and be0n. note: if the local device decoder is used in either synchronous or asynchronous transfers, ldevn will be asserted to indicate that the ksz8841m is successfully targeted. the signal ldevn is a combinatorial decode of aen and a[15:4]. asynchronous interface for asynchronous transfers, the asynchronous dedicated signals rdn (for read) or wrn (for write) toggle, but the synchronous dedicated signals cyclen, swr, and rdyrtnn are de-asserted and stay at the same logic level throughout the entire asynchronous transfer. there is no data burst support for asynchronous transfer. all asynchronous transfers are single-data transfers. the biu, however, provides flexible asynchronous interfacing to communicate with various applications and architectures. three major ways of interfacing with the system (host) are. 1. interfacing with the system/host relying on local device decoding and having stable address throughout the whole transfer: the typical example for this application is isa-like bus interface using latched address signals as shown in figure 13. no additional address latch is required, therefore adsn should be connected low. the biu decodes a[15:4] and qualifies with aen (address enable) to determine if the ksz8841m device is the intended target. the host utilizes the rising edge of rdn to latch read data and the biu will use rising edge of wrn to latch write data. interfacing with the system/host relying on local device decoding but not having stable address throughout the entire transfer: the typical example for this application is eisa-like bus (non-burst) interface as shown in the figure 14. this type of interface requires adsn to latch the address on the rising edge. the biu decodes latched a[15:4] and qualifies with aen to determine if the ksz8841m device is the intended target. the data transfer is the same as the first case. interfacing with the system/host relying on central decoding (ksz8841-32mql only). the typical example for this application is for an embedded processor having a central decoder on the system board or within the processor. connecting the chip select (cs) from system/host to datacsn bypasses the local device decoder. when the datacsn is asserted, it only allows access to the data register in 32 bits and be3n, be2n, be1n, and be0n are ignored as shown in the figure 15. no other registers can be accessed by asserting datacsn. the data transfer is the same as in the first case. independent of the type of asynchronous interface used. to insert a wait state, the biu will assert ardy to prolong the cycle.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 36 m9999-102207-1.6 synchronous interface for synchronous transfers, the synchronous dedicated signals cyclen, swr, and rdyrtnn will toggle but the asynchronous dedicated signals rdn and wrn are de-asserted and stay at the same logic level throughout the entire synchronous transfer. the synchronous interface mainly supports two applications, one for vlbus-like and the other for eisa-like (dma type c) burst transfers. the vlbus-like interface supports only single-data transfer. the pin option vlbusn determines if it is a vlbus-like or eisa-like burst transfer ? if vlbusn = 0, the interface is for vlbus-like transfer; if vlbusn = 1, the interface is for eisa-like burst transfer. for vlbus-like transfer interface (vlbusn = 0): this interface is used in an architecture in which the device?s local decoder is utilized; that is, the biu decodes latched a[15:4] and qualifies with aen (address enable) to determine if the ksz8841m device is the intended target. no burst is supported in this application. the m/nio signal connection in vlbus is routed to aen. the cyclen in this application is used to sample the swr signal when it is asserted. usually, cyclen is one clock delay of adsn. there is a handshaking process to end the cycle of vlbus-like transfers. when the ksz8841m is ready to finish the cycle, it asserts srdyn . the system/host acknowledges srdyn by asserting rdyrtnn after the system/host has latched the read data. the ksz8841m holds the read data until rdyrtnn is asserted. the timing waveform is shown in figures 19 and 20. for eisa-like burst transfer interface (vlbusn = 1): the swr is connected to iorc# in eisa to indicate the burst read and cyclen is connected to iowc# in eisa to indicate the burst write. note that in this application, both the system/host/memory and ksz8841m are capable of inserting wait states. for system/host/memory to insert a wait state, assert the rdyrtnn signal; for the ksz8841m to insert the wait state, assert the srdyn signal. the timing waveform is shown in figures 17 and 18. biu summation figure 10 shows the mapping from isa-like, eisa-like and vlbus-like transactions to the chip?s biu. figure 11 shows the connection for different data bus sizes. note: for the 8-bit data bus mode, the internal inverter is enabled and connected between be0n and be1n, so an even address will enable the be0n and an odd address will enable the be1n.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 37 m9999-102207-1.6 ksz8841m biu asynchronous interface synchronous interface address latch no addr latch (adsn = 0) central decode local decode address latch central decode (vlbusn = 1) local decode (vlbusn = 0) host interface host interface host interface host interface isa eisa vlbus burst non-burst note: to use datacsn & 32-bit only for central decode figure 10. mapping from the isa, eisa, and vlbus to the ksz8841m bus interface d[7:0] d[15:8] d[23:16] d[31:24] gnd hd[7:0] nhbe[0] nhbe[2] nhbe[3] hd[15:8] nhbe[1] hd[23:16] hd[31:24] a[15:2] a[1] d[7:0] d[15:8] be0n be1n 8-bit data bus ha[1] ha[15:2] hd[7:0] ha[0] vdd a[15:2] a[1] d[7:0] d[15:8] be0n be1n 16-bit data bus (for example: isa-like) ha[1] ha[15:2] hd[7:0] ha[0] nsbhe a[15:2] a[1] be0n be1n be2n be3n 32-bit data bus (for example: eisa-like) ha[15:2] hd[15:8] ksz8841-16 ksz8841-16 ksz8841-32 figure 11. ksz8841m 8-bit, 16-bit, and 32-bit data bus connections biu implementation principles since ksz8841m is an i/o device with 16 addressable locations, address decoding is based on the values of a15-a4 and aen. whenever datacsn is asserted, the address decoder is disabled and a 32-bit transfer to data register is assumed (be3n ? be0n are ignored). if address latching is required, the address is latched on the rising edge of adsn and is transparent when adsn=0. 1. byte, word, and double word data buses and accesses (transfers) are supported. 2. internal byte swapping is not implemented and word swapping is supported internally. refer to figure 11 for the appropriate 8-bit, 16-bit, and 32-bit data bus connection. 3. since independent sets of synchronous and asynchronous signals are provided, synchronous and asynchronous cycles can be mixed or interleaved as long as they are not active simultaneously.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 38 m9999-102207-1.6 4. the asynchronous interface uses rdn and wrn signal strobes for data latching. if necessary, ardy is de- asserted on the leading edge of the strobe. 5. the vlbus-like synchronous interface uses bclk, adsn, and swr and cyclen to control read and write operations and generate srdyn to insert the wait state, if necessary, when vlbusn = 0. for read, the data must be held until rdyrtnn is asserted. the eisa-like burst transfer is supported using synchronous interface signals and datacsn when i/o signal vlbusn = 1. both the system/host/memory and ksz8841m are capable of inserting wait states. to set the system/host/memory to insert a wait state, assert rdyrtnn signal. to set the ksz8841m to insert a wait state, assert srdyn signal. queue management unit (qmu) the queue management unit (qmu) manages packet traffic between the mac/phy interface and the system host. it has built-in packet memory for receive and transmit functions called txq (transmit queue) and rxq (receive queue). each queue contains 4kb of memory for back-to-back, non-blocking frame transfer performance. it provides a group of control registers for system control, frame status registers for current packet transmit/receive status, and interrupts to inform the host of the real time tx/rx status. transmit queue (txq) frame format the frame format for the transmit queue is shown in the following table 3. the first word contains the control information for the frame to transmit. the second word is used to specify the total number of bytes of the frame. the packet data follows. the packet data area holds the frame itself. it may or may not include the crc checksum depending upon whether hardware crc checksu m generation is enabled. multiple frames can be pipelined in both the transmit queue and receive queue as long as there is enough queue memory, thus avoiding overrun. for each transmitted frame, the transmit status information for the frame is located in the txsr register. packet memory address offset bit 15 bit 0 2 nd byte 1 st byte 0 control word 2 byte count 4 - up transmit packet data (maximum size is 1916) table 3. frame format for transmit queue since multiple packets can be pipelined into the tx packet memory for transmit, the transmit status reflects the status of the packet that is currently being transferred on the mac interface, which may or may not be the last queued packet in the tx queue. the transmit control word is the first 16-bit word in the tx packet memory, followed by a 16-bit byte count. it must be word aligned. each control word corresponds to one tx packet. table 4 gives the transmit control word bit fields. bit description 15 txic transmit interrupt on completion when this bit is set, the ksz8841m sets the transmit interrupt after the present frame has been transmitted. 14-6 reserved. 5-0 txfid transmit frame id this field specifies the frame id that is used to identify the frame and its associated status information in the transmit status register. table 4. transmit control word bit fields
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 39 m9999-102207-1.6 the transmit byte count specifies the total number of bytes to be transmitted from the txq. its format is given in table 5. bit description 15-11 reserved. 10-0 txbc transmit byte count transmit byte count. hardware uses the byte count information to conserve the tx buffer memory for better utilization of the packet memory. note: the hardware behavior is unknown if an incorrect byte count information is written to this field. writing a 0 value to this field is not permitted. table 5. transmit byte count format the data area contains six bytes of destination address (da) followed by six bytes of source address (sa), followed by a variable-length number of bytes. on transmit, all bytes are provided by the cpu, including the source address. the ksz8841m does not insert its own sa. the 802.3 frame length word (frame type in ethernet) is not interpreted by the ksz8841m. it is treated transparently as data both for transmit operations. receive queue (rxq) frame format the frame format for the receive queue is shown in table 6. the first word contains the status information for the frame received. the second word is the total number of bytes of the rx frame. following that is the packet data area. the packet data area holds the frame itself. it may or ma y not include the crc checksum depending on whether hardware crc stripping is enabled. packet memory address offset bit 15 bit 0 2 nd byte 1 st byte 0 status word 2 byte count 4 - up receive packet data (maximum size is 1916) table 6. frame format for receive queue for receive, the packet receive status always reflects the receive status of the packet received in the current rx packet memory (see table 7). the rxsr register indicates the status of the current received frame. bit description 15 rxfv receive frame valid when set, this field indicates that the present frame in the receive packet memory is valid. the status information currently in this location is also valid. when clear, it indicates that there is either no p ending receive frame or that the current frame is still in the process of receiving. 14-8 reserved. 7 rxbf receive broadcast frame when set, it indicates that this frame has a broadcast address. 6 rxmf receive multicast frame when set, it indicates that this frame has a multicast address (including the broadcast address). 5 rxuf receive unicast frame when set, it indicates that this frame has a unicast address. 4 reserved. 3 rxft receive frame type when set, it indicates that the frame is an ethernet-type frame (frame length is greater than 1500 bytes). when clear, it indicates that the frame is an ieee 802.3 frame. this bit is not valid for runt frames. 2 rxtl receive frame too long when set, it indicates that the frame length exceeds the maximum size of 1518 bytes. frames that are too long are passed to the host only if the pass bad frame bit is set. note: frame too long is only a frame length indication and does not cause any frame truncation.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 40 m9999-102207-1.6 bit description 1 rxrf receive runt frame when set, it indicates that a frame was damaged by a collision or had a premature termination before the collision window passed. runt frames are passed to the host only if the pass bad frame bit is set. 0 rxce receive crc error when set, it indicates that a crc error has occurred on the current received frame. crc error frames are passed to the host only if the pass bad frame bit is set. table 7. rxq receive packet status word table 8 gives the format of the rx byte count field. bit description 15-11 reserved 10-0 rxbc receive byte count receive byte count up to 1916 bytes table 8. rxq receive packet byte count word eeprom interface it is optional in the ksz8841m to use an external eeprom. in the case that an eeprom is not used, the eeen pin must be tied low or floating. an external serial eeprom with a standard microwire bus interface is used for non-volatile storage of information such as the host mac address, base address, and default configuration settings. the ksz8841m can detect if the eeprom is a 1kb (93c46) or 4kb (93c66) eeprom device (the 93c46 and the 93c66 are typical eeprom devices). the eeprom is organized as 16-bit mode. if the eeen pin is pulled high, then the ksz8841m performs an automatic read of the external eeprom words 0h to 6h after the de-assertion of reset. the eeprom values are placed in certain host-accessible registers. eeprom read/write functions can also be performed by software read/writes to the eepcr registers. the ksz8841m eeprom format is given in table 9. word 15 8 7 0 0h base address 1h host mac address byte 2 host mac address byte 1 2h host mac address byte 4 host mac address byte 3 3h host mac address byte 6 host mac address byte 5 4h reserved 5h reserved 6h configparam (see table 10) 7h-3fh not used for ksz8841m (available for user to use) table 9. ksz8841m eeprom format
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 41 m9999-102207-1.6 the format for configparam is shown in table 10. bit bit name description 15 reserved reserved 14 no_srst no soft reset when this bit is set, indicates that ksz8841m transitioning from d3_hot to d0 because of powerstate commands do not perform an internal reset. configuration context is preserved. upon transition from the d3_hot to the d0 initialized state, no additional operating system intervention is required to preserve configuration context beyond writing the powerstate bits. when this bit is clear, ksz8841m performs an internal reset upon transitioning from d3_hot to d0 via software control of the powerstate bits. configuration context is lost when performing the soft reset. upon trasition from the d3_hot to the d0 state, full reinitialization sequence is needed to return the device to d0 initialized. regardless of this bit, devices that transition from d3_hot to d0 by a system or bus segment reset will return to the device state d0 uninitialized with only pme context preserved if pme is supported and enabled. this bit is loaded to bit 3 of pmcs register 13 reserved reserved. 12 pme_d2 pme support d2 when this bit is set, the ksz8841m asserts pme event (pin 14) when the ksz8841m is in d2 state and pme_en is set. otherwise, the ksz8841m does not assert pme event when the ksz8841m is in d2 state. this bit is loaded to bit 13 of pmcr register 11 pme_d1 pme support d1 when this bit is set, the ksz8841m asserts pme event (pin 14) when the ksz8841m is in d1 state and pme_en is set. otherwise, the ksz8841m does not assert pme event when the ksz8841m is in d1 state. this bit is loaded to bit 12 of pmcr register. 10 d2_sup d2 support when this bit is set, the ksz8841m supports d2 power state. this bit is loaded to bit 10 of pmcr register. 9 d1_sup d1 support when this bit is set, the ksz8841m supports d1 power state. this bit is loaded to bit 9 of pmcr register. 8-2 reserved reserved. 1 clock_rate internal clock rate selection 0: 125 mhz 1: 25 mhz note: at power up, this chip operates on 125 mhz clock. the internal frequency can be dropped to 25 mhz via the external eeprom. 0 asyn_8bit async 8-bit bus select 1= bus is configured for 16-bit width 0= bus is configured for 8-bit width this bit is loaded to bit 0 of pmcr register (32-bit width, ksz8841-32mql, don?t care this bit setting) table 10. configparam word in eeprom format
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 42 m9999-102207-1.6 loopback support the ksz8841m provides near-end (remote) loopback support for remote diagnostic of failure. in loopback mode, the speed at the phy port will be set to 100base-tx full-duplex mode. near-end (remote) loopback near-end (remote) loopback is conducted at phy port 1of the ksz8841m. the loopback path starts at the phy port?s receive inputs (rxp1/rxm1), wraps around at the same phy port?s pmd/pma, and ends at the phy port?s transmit outputs (txp1/txm1). bit [1] of register p1phyctrl is used to enable near-end loopback for port 1. alternatively, bit [9] of register p1scslmd can also be used to enable near-end loopback. the ports 1 near-end loopback path is illustrated in the following figure 12. bus i/f unit qmu/dma rxq/txq mac1 pcs1 pmd1/pma1 rxp1 / rxm1 txp1 / txm1 phy port 1 near-end (remote) loopback figure 12. phy port 1 near-end (remote) loopback path
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 43 m9999-102207-1.6 cpu interface i/o registers the ksz8841m provides an eisa-like, isa-like, or vlbus-like bus interface for the cpu to access its internal i/o registers. i/o registers serve as the address that the microprocessor uses when communicating with the device. this is used for configuring operational settings, reading or writing control, status information, and transferring packets by reading and writing through the packet data registers. i/o registers input/output (i/o) registers are limited to 16 locations as required by most isa bus-based systems; therefore, registers are assigned to different banks. the last word of the i/o register locations (0xe - 0xf) is shared by all banks and can be used to change the bank in use. the following i/o space mapping tables apply to 8, 16 or 32-bit bus products. depending upon the bus interface used and byte enable signals (be[3:0]n control byte access), each i/o access can be performed as an 8-bit, 16-bit, or 32-bit operation. (the ksz8841m is not limited to 8/16-bit performance and 32-bit read/write are also supported).
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 44 m9999-102207-1.6 internal i/o space mapping i/o register location bank location 32-bit 16-bit 8-bit bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 0x0 base address [7:0] host mac address low [7:0] on-chip bus control [7:0] wakeup frame0 crc0 [7:0] wakeup frame1 crc0 [7:0] wakeup frame2 crc0 [7:0] wakeup frame3 crc0 [7:0] 0x0 - 0x1 0x1 base address [15:8] reserved host mac address low [15:8] on-chip bus control [15:8] wakeup frame0 crc0 [15:8] wakeup frame1 crc0 [15:8] wakeup frame2 crc0 [15:8] wakeup frame3 crc0 [15:8] 0x2 host mac address mid [7:0] eeprom control [7:0] wakeup frame0 crc1 [7:0] wakeup frame1 crc1 [7:0] wakeup frame2 crc1 [7:0] wakeup frame3 crc1 [7:0] 0x0 to 0x3 0x2 - 0x3 0x3 reserved reserved host mac address mid [15:8] eeprom control [15:8] wakeup frame0 crc1 [15:8] wakeup frame1 crc1 [15:8] wakeup frame2 crc1 [15:8] wakeup frame3 crc1 [15:8] 0x4 qmu rx flow control watermark [7:0] host mac address high [7:0] memory bist info [7:0] wakeup frame0 byte mask0 [7:0] wakeup frame1 byte mask0 [7:0] wakeup frame2 byte mask0 [7:0] wakeup frame3 byte mask0 [7:0] 0x4 - 0x5 0x5 qmu rx flow control watermark [15:8] reserved host mac address high [15:8] memory bist info [15:8] wakeup frame0 byte mask0 [15:8] wakeup frame1 byte mask0 [15:8] wakeup frame2 byte mask0 [15:8] wakeup frame3 byte mask0 [15:8] 0x6 bus error status [7:0] global reset [7:0] wakeup frame0 byte mask1 [7:0] wakeup frame1 byte mask1 [7:0] wakeup frame2 byte mask1 [7:0] wakeup frame3 byte mask1 [7:0] 0x4 to 0x7 0x6 - 0x7 0x7 bus error status [15:8] reserved reserved global reset [15:8] wakeup frame0 byte mask1 [15:8] wakeup frame1 byte mask1 [15:8] wakeup frame2 byte mask1 [15:8] wakeup frame3 byte mask1 [15:8] 0x8 bus burst length [7:0] power management capabilities [7:0] wakeup frame0 byte mask2 [7:0] wakeup frame1 byte mask2 [7:0] wakeup frame2 byte mask2 [7:0] wakeup frame3 byte mask2 [7:0] 0x8 - 0x9 0x9 bus burst length [15:8] reserved reserved power management capabilities [15:8] wakeup frame0 byte mask2 [15:8] wakeup frame1 byte mask2 [15:8] wakeup frame2 byte mask2 [15:8] wakeup frame3 byte mask2 [15:8] 0xa wakeup frame control [7:0] wakeup frame0 byte mask3 [7:0] wakeup frame1 byte mask3 [7:0] wakeup frame2 byte mask3 [7:0] wakeup frame3 byte mask3 [7:0] 0x8 to 0xb 0xa - 0xb 0xb reserved wakeup frame control [15:8] wakeup frame0 byte mask3 [15:8] wakeup frame1 byte mask3 [15:8] wakeup frame2 byte mask3 [15:8] wakeup frame3 byte mask3 [15:8] 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8]
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 45 m9999-102207-1.6 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 bank 15 0x0 0x0 - 0x1 0x1 reserved 0x2 0x0 to 0x3 0x2 - 0x3 0x3 reserved 0x4 0x4 - 0x5 0x5 reserved 0x6 0x4 to 0x7 0x6 - 0x7 0x7 reserved 0x8 0x8 - 0x9 0x9 reserved 0xa 0x8 to 0xb 0xa - 0xb 0xb reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8]
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 46 m9999-102207-1.6 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 16 bank 17 bank 18 bank 19 bank 20 bank 21 bank 22 bank 23 0x0 transmit control [7:0] txq command [7:0] interrupt enable [7:0] multicast table 0 [7:0] 0x0 - 0x1 0x1 transmit control [15:8] txq command [15:8] interrupt enable [15:8] multicast table 0 [15:8] reserved 0x2 transmit status [7:0] rxq command [7:0] interrupt status [7:0] multicast table 1 [7:0] 0x0 to 0x3 0x2 - 0x3 0x3 transmit status [15:8] rxq command [15:8] interrupt status [15:8] multicast table 1 [15:8] reserved 0x4 receive control [7:0] tx frame data pointer [7:0] receive status [7:0] multicast table 2 [7:0] 0x4 - 0x5 0x5 receive control [15:8] tx frame data pointer [15:8] receive status [15:8] multicast table 2 [15:8] reserved 0x6 rx frame data pointer [7:0] receive byte counter [7:0] multicast table 3 [7:0] 0x4 to 0x7 0x6 - 0x7 0x7 reserved rx frame data pointer [15:8] receive byte counter [15:8] multicast table 3 [15:8] reserved 0x8 txq memory information [7:0] qmu data low [7:0] early transmit [7:0] power management control/status [7:0] 0x8 - 0x9 0x9 txq memory information [15:8] qmu data low [15:8] early transmit [15:8] power management control/status [15:8] reserved 0xa rxq memory information [7:0] qmu data high [7:0] early receive [7:0] 0x8 to 0xb 0xa - 0xb 0xb rxq memory information [15:8] qmu data high [15:8] early receive [15:8] reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8]
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 47 m9999-102207-1.6 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 24 bank 25 bank 26 bank 27 bank 28 bank 29 bank 30 bank 31 0x0 0x0 - 0x1 0x1 reserved 0x2 0x0 to 0x3 0x2 - 0x3 0x3 reserved 0x4 0x4 - 0x5 0x5 reserved 0x6 0x4 to 0x7 0x6 - 0x7 0x7 reserved 0x8 0x8 - 0x9 0x9 reserved 0xa 0x8 to 0xb 0xa - 0xb 0xb reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8]
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 48 m9999-102207-1.6 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 32 bank 33 bank 34 bank 35 bank 36 bank 37 bank 38 bank 39 0x0 chip id and enable [7:0] 0x0 - 0x1 0x1 chip id and enable [15:8] reserved 0x2 0x0 to 0x3 0x2 - 0x3 0x3 reserved 0x4 0x4 - 0x5 0x5 reserved 0x6 0x4 to 0x7 0x6 - 0x7 0x7 reserved 0x8 0x8 - 0x9 0x9 reserved 0xa chip global control [7:0] 0x8 to 0xb 0xa - 0xb 0xb chip global control [15:8] reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8]
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 49 m9999-102207-1.6 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 40 bank 41 bank 42 bank 43 bank 44 bank 45 bank 46 bank 47 0x0 indirect access control. [7:0] phy1 mii- register basic control [7:0] phy1 linkmd control/status [7:0] 0x0 - 0x1 0x1 reserved indirect access control. [15:8] reserved phy1 mii- register basic control [15:8] reserved phy1 linkmd control/status [15:8] 0x2 indirect access data 1 [7:0] phy1 mii- register basic status [7:0] phy1 special control/status [7:0] 0x0 to 0x3 0x2 - 0x3 0x3 reserved indirect access data 1 [15:8] reserved phy1 mii- register basic status [15:8] reserved phy1 special control/status [15:8] 0x4 indirect access data 2 [7:0] phy1 phyid low [7:0] 0x4 - 0x5 0x5 reserved indirect access data 2 [15:8] reserved phy1 phyid low [15:8] reserved 0x6 indirect access data 3 [7:0] phy1 phyid high [7:0] 0x4 to 0x7 0x6 - 0x7 0x7 reserved indirect access data 3 [15:8] reserved phy1 phyid high [15:8] reserved 0x8 indirect access data 4 [7:0] phy1 a.n. advertisement [7:0] 0x8 - 0x9 0x9 reserved indirect access data 4 [15:8] reserved phy1 a.n. advertisement [15:8] reserved 0xa indirect access data 5 [7:0] phy1 a.n. link partner ability [7:0] 0x8 to 0xb 0xa - 0xb 0xb reserved indirect access data 5 [15:8] reserved phy1 a.n. link partner ability [15:8] reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8]
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 50 m9999-102207-1.6 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 48 bank 49 bank 50 bank 51 bank 52 bank 53 bank 54 bank 55 0x0 port 1 phy special control/status, linkmd [7:0] 0x0 - 0x1 0x1 reserved port 1 phy special control/status, linkmd [15:8] reserved 0x2 port 1 control 4 [7:0] 0x0 to 0x3 0x2 - 0x3 0x3 reserved port 1 control 4 [15:8] reserved 0x4 port 1 status [7:0] 0x4 - 0x5 0x5 reserved port 1 status [15:8] reserved 0x6 0x4 to 0x7 0x6 - 0x7 0x7 reserved 0x8 0x8 - 0x9 0x9 reserved 0xa 0x8 to 0xb 0xa - 0xb 0xb reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8]
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 51 m9999-102207-1.6 internal i/o space mapping (continued) i/o register location bank location 32-bit 16-bit 8-bit bank 56 bank 57 bank 58 bank 59 bank 60 bank 61 bank 62 bank 63 0x0 0x0 - 0x1 0x1 reserved 0x2 0x0 to 0x3 0x2 - 0x3 0x3 reserved 0x4 0x4 - 0x5 0x5 reserved 0x6 0x4 to 0x7 0x6 - 0x7 0x7 reserved 0x8 0x8 - 0x9 0x9 reserved 0xa 0x8 to 0xb 0xa - 0xb 0xb reserved 0xc 0xc - 0xd 0xd reserved 0xe bank select [7:0] 0xc to 0xf 0xe - 0xf 0xf bank select [15:8]
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 52 m9999-102207-1.6 register map: mac and phy do not write to bit values or to registers defined as reserved. manipulating reserved bits or registers causes unpredictable and often fatal results. if the user wants to write to these reserved bits, the user has to read back these reserved bits (ro or rw) first, then ?or? with the read value of the reserved bits and write back to these reserved bits. bit type definition ro = read only. rw = read/write. w1c = write 1 to clear (writing a one to this bit clears it). bank 0-63 bank select register (0x0e): bsr (same location in all banks) the bank select register is used to select or to switch between different sets of register banks for i/o access. there are a total of 64 banks available to select, including the built-in switch engine registers. bit default value r/w description 15-6 0x000 ro reserved 5-0 0x00 r/w bsa bank select address bits bsa bits select the i/o register bank in use. this register is always accessible regardless of the register bank currently selected. notes: the bank select register can be accessed as a doubleword (32-bit) at offset 0xc, as a word (16-bit) at offset 0xe, or as a byte (8-bit) at offset 0xe. a doubleword write to offset 0xc writes to the bank select register but does not write to registers 0xc and 0xd; it only writes to register 0xe. bank 0 base address register (0x00): bar this register holds the base address for decoding a device access. its value is loaded from the external eeprom (0x0h) upon a power-on reset if the eeprom enable (eeen) pin is tied to high. its value can also be modified after reset. writing to this register does not store the value into the eeprom. when the eeen pin is tied to low, the default base address is 0x300. bit default value r/w description 15-8 0x03 if eeen is low or, the value from eeprom if eeen is high rw barh base address high these bits are compared against the address on the bus addr[15:8] to determine the base for the ksz8841m registers. 7-5 0x00 if eeen is low or, the value from eeprom if eeen is high rw barl base address low these bits are compared against the address on the bus addr[7:5] to determine the base for the ksz8841m registers. 4-0 0x00 ro reserved
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 53 m9999-102207-1.6 bank 0 qmu rx flow control high watermark configuration register (0x04): qrfcr this register contains the user defined qmu rx queue high watermark configuration bit as below. bit default value r/w description 15-13 0x0 ro reserved 12 0 rw qmu rx flow control high watermark configuration 0: 3 kbytes 1: 2 kbytes 11-0 0x000 ro reserved bank 0 bus error status register (0x06): besr this register flags the different kinds of errors on the host bus. bit default value r/w description 15 0 ro ibec illegal byte enable combination 1: illegal byte enable combination occurs. the illegal combination value can be found from bit 14 to bit 11. 0: legal byte enable combination. write 1 to clear. 14-11 - ro ibecv illegal byte enable combination value bit 14: byte enable 3. bit 13: byte enable 2. bit 12: byte enable 1. bit 11: byte enable 0. this value is valid only when bit 15 is set to 1. 10 0 ro ssaxfer simultaneous synchronous and asnychronous transfers 1: synchronous and asnychronous transfers occur simultaneously. 0: normal. write 1 to clear. 9-0 0x000 ro reserved. bank 0 bus burst length register (0x08): bblr before the burst can be sent, the burst length needs to be programmed. bit default value r/w description 15 0 ro reserved. 14-12 0x0 rw brl burst length (for burst read and write) 000: single. 011: fixed burst read length of 4. 101: fixed burst read length of 8. 111: fixed burst read length of 16. 11-0 0x000 ro reserved. bank 1: reserved except bank select register (0xe).
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 54 m9999-102207-1.6 bank 2 host mac address register low (0x00): marl this register along with the other two host mac address registers are loaded starting at word location 0x1 of the eeprom upon hardware reset. the software driver can modify the register, but it will not modify the original host mac address value in the eeprom. these six bytes of host mac address in external eeprom are loaded to these three registers as mapping below: marl[15:0] = eeprom 0x1(mac byte 2 and 1) marm[15:0] = eeprom 0x2(mac byte 4 and 3) marh[15:0] = eeprom 0x3(mac byte 6 and 5) the host mac address is used to define the individual destination address that the ksz8841m responds to when receiving frames. network addresses are generally expressed in the form of 01:23:45:67:89:ab, where the bytes are received from left to right, and the bits within each byte are received from right to left (lsb to msb). for example, the actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101. these three registers value for host mac address 01:23:45:67:89:ab will be held as below: marl[15:0] = 0x89ab marm[15:0] = 0x4567 marh[15:0] = 0x0123 the following table shows the register bit fields for low word of host mac address. bit default value r/w description 15-0 - rw marl mac address low the least significant word of the mac address. bank 2 host mac address register middle (0x02): marm the following table shows the register bit fields for middle word of host mac address. bit default value r/w description 15-0 - rw marm mac address middle the middle word of the mac address. bank 2 host mac address register high (0x04): marh the following table shows the register bit fields for high word of host mac address. bit default value r/w description 15-0 - rw marh mac address high the most significant word of the mac address.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 55 m9999-102207-1.6 bank 3 on-chip bus control register (0x00): obcr this register controls the on-chip bus speed for the ksz8841m. it is used for power management when the external host cpu is running at a slow frequency. the default of the on-chip bus speed is 125 mhz without eeprom. when the external host cpu is running at a higher clock rate, the on-chip bus should be adjusted for the best performance. bit default value r/w description 15-2 - ro reserved. 1-0 0x0 rw obsc on-chip bus speed control 00: 125mhz. 01: 62.5mhz. 10: 41.66mhz. 11: 25mhz. note: when external eeprom is enabled, the bit 1 in configparm word (0x6h) is used to contol this speed as below: bit 1 = 0 , this value will be 00 for 125 mhz. bit 1 = 1 , this value will be 11 for 25 mhz. (user still can write these two bits to change speed after eeprom data loaded) bank 3 eeprom control register (0x02): eepcr to support an external eeprom, tie the eeprom enable (eeen) pin to high; otherwise, tie it to low. if an external eeprom is not used, the default chip base address (0x300), and the software programs the host mac address. if an eeprom is used in the design (eeprom enable pin to high), the chip base address and host mac address are loaded from the eeprom immediately after reset. the ksz8841m allows the software to access (read and write) the eeprom directly; that is, the eeprom access timing can be fully controlled by the software if the eeprom software access bit is set. bit default value r/w description 15-5 - ro reserved. 4 0 rw eesa eeprom software access 1: enable software to access eeprom through bit 3 to bit 0. 0: disable software to access eeprom. 3 - ro eecb eeprom status bit data receive from eeprom. this bit directly reads the eedi pin. 2-0 0x0 rw eecb eeprom control bits bit 2: data transmit to eeprom. this bit directly controls the device?s eedo pin. bit 1: serial clock. this bit directly controls the device?s eesk pin. bit 0: chip select for eeprom. this bit directly controls the device?s eecs pin.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 56 m9999-102207-1.6 bank 3 memory bist info register (0x04): mbir bit default value r/w description 15-13 0x0 ro reserved. 12 - ro txmbf tx memory bist finish when set, it indicates the memory built in self test completion for the tx memory. 11 - ro txmbfa tx memory bist fail when set, it indicates the memory built in self test has failed. 10-5 - ro reserved 4 - ro rxmbf rx memory bist finish when set, it indicates the memory built in self test completion for the rx memory. 3 - ro rxmbfa rx memory bist fail when set, it indicates the memory built in self test has failed. 2-0 - ro reserved. bank 3 global reset register (0x06): grr this register controls the global reset function with information programmed by the cpu. bit default value r/w description 15-1 0x0000 ro reserved. 0 0 rw global soft reset = 1 software reset is active. = 0 software reset is inactive. software reset will affect phy, mac, qmu, dma, and the switch core, only the biu (base address registers) remains unaffected by a software reset. bank 3 power management capabilities register (0x08): pmcr this register is a read-only register that provides information on the k8841m power management capabilities. these bits are automatically downloaded from configparam word of eeprom , if pin eeen is high (enabled eeprom) bit default value r/w description 15 0 ro pme support d3 (cold) this bit defaults to 0, so the ksz8841m does not support d3(cold) 14 1 ro pme support d3 (hot) this bit is 1 only,it is indicating that the ksz8841m can assert pme event (pmen pin 14) in d3(hot) power state.(see bit1:0 in pmcs register) 13 0 ro pme support d2 if this bit is set, the wake-up signals will assert pme event (pmen pin 14) when the ksz8841m is in d2 power state and pme_en (see bit8 in pmcs register) is set. otherwise, the ksz8841m does not assert pme event (pmen pin 14) when the ksz8841m is in d2 power state. the value of this bit is loaded from the pme_d2 bit of 0x6 in the serial eeprom (without an eeprom, this bit defaults to 0). 12 0 ro pme support d1 if this bit is set, the wake-up signals will assert pme event (pmen pin 14) when the ksz8841m is in d1 power state and pme_en (see bit8 in pmcs register) is set. otherwise, the ksz8841m does not assert pme event (pmen pin 14) when the ksz8841m is in d1 power state. the value of this bit loaded from the pme_d1 bit of 0x6 in the serial eeprom (without an eeprom, this bit defaults to 0). 11 0 ro pme support d0 this bit defaults to 0, it is indicating that the ksz8841m does not assert pme event
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 57 m9999-102207-1.6 bit default value r/w description (pmen pin 14) in d0 power state. 10 0 ro d2 support if this bit is set, it indicates that the ksz8841m support d2 power state. the value of this bit is loaded from the d2_sup bit of 0x6 in the serial eeprom (without an eeprom, this bit defaults to 0). 9 0 ro d1 support if this bit is set, it indicates that the ksz8841m support d1 power state. the value of this bit is loaded from the d1_sup bit of 0x6 in the serial eeprom (without an eeprom, this bit defaults to 0). 8-1 - ro reserved. 0 - ro bus configuration (only for ksz8841-16mql device) 1: bus width is 16 bits. 0: bus width is 8 bits. (this bit, asyn_8bit, is only avaiable when eeprom is enabled) bank 3 wakeup frame control register (0x0a): wfcr this register holds control information programmed by the cpu to control the wake up frame function. bit default value r/w description 15-8 0x00 ro reserved. 7 0 rw mprxe magic packet rx enable when set, it enables the magic packet pattern detection. when reset, the magic packet pattern detection is disabled. 6-4 0x0 ro reserved. 3 0 rw wf3e wake up frame 3 enable when set, it enables the wake up frame 3 pattern detection. when reset, the wake up frame 3 pattern detection is disabled. 2 0 rw wf2e wake up frame 2 enable when set, it enables the wake up frame 2 pattern detection. when reset, the wake up frame 2 pattern detection is disabled. 1 0 rw wf1e wake up frame 1 enable when set, it enables the wake up frame 1 pattern detection. when reset, the wake up frame 1 pattern detection is disabled. 0 0 rw wf0e wake up frame 0 enable when set, it enables the wake up frame 0 pattern detection. when reset, the wake up frame 0 pattern detection is disabled.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 58 m9999-102207-1.6 bank 4 wakeup frame 0 crc0 register (0x00): wf0crc0 this register contains the expected crc values of the wake up frame 0 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard; it is taken over the bytes specified in the wake up byte mask registers. bit default value r/w description 15-0 0x0000 rw wf0crc0 wake up frame 0 crc (lower 16 bits) the expected crc value of a wake up frame 0 pattern. bank 4 wakeup frame 0 crc1 register (0x02): wf0crc1 this register contains the expected crc values of the wake up frame 0 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard; it is taken over the bytes specified in the wake up byte mask registers. bit default value r/w description 15-0 0 rw wf0crc1 wake up frame 0 crc (upper 16 bits). the expected crc value of a wake up frame 0 pattern. bank 4 wakeup frame 0 byte mask 0 register (0x04): wf0bm0 this register contains the first 16 bytes mask values of the wake up frame 0 pattern. setting bit 0 selects the first byte of the wake up frame 0, setting bit 15 selects the 16th byte of the wake up frame 0. bit default value r/w description 15-0 0 rw wf0bm0 wake up frame 0 byte mask 0 the first 16 bytes mask of a wake up frame 0 pattern. bank 4 wakeup frame 0 byte mask 1 register (0x06): wf0bm1 this register contains the next 16 bytes mask values of the wake up frame 0 pattern. setting bit 0 selects the 17th byte of the wake up frame 0. setting bit 15 selects the 32nd byte of the wake up frame 0. bit default value r/w description 15-0 0 rw wf0bm1 wake up frame 0 byte mask 1. the next 16 bytes mask covering bytes 17 to 32 of a wake up frame 0 pattern. bank 4 wakeup frame 0 byte mask 2 register (0x08): wf0bm2 this register contains the next 16 bytes mask values of the wake up frame 0 pattern. setting bit 0 selects the 33rd byte of the wake up frame 0. setting bit 15 selects the 48th byte of the wake up frame 0. bit default value r/w description 15-0 0 rw wf0bm2 wake-up frame 0 byte mask 2. the next 16 bytes mask covering bytes 33 to 48 of a wake-up frame 0 pattern.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 59 m9999-102207-1.6 bank 4 wakeup frame 0 byte mask 3 register (0x0a): wf0bm3 this register contains the last 16 bytes mask values of the wake up frame 0 pattern. setting bit 0 selects the 49th byte of the wake up frame 0. setting bit 15 selects the 64th byte of the wake up frame 0. bit default value r/w description 15-0 0 rw wf0bm3 wake-up frame 0 byte mask 3. the last 16 bytes mask covering bytes 49 to 64 of a wake-up frame 0 pattern. bank 5 wakeup frame 1 crc0 register (0x00): wf1crc0 this register contains the expected crc values of the wake up frame 1 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard; it is taken over the bytes specified in the wake up byte mask registers. bit default value r/w description 15-0 0 rw wf1crc0 wake-up frame 1 crc (lower 16 bits). the expected crc value of a wake-up frame 1 pattern. bank 5 wakeup frame 1 crc1 register (0x02): wf1crc1 this register contains the expected crc values of the wake up frame 1 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. bit default value r/w description 15-0 0 rw wf1crc1 wake-up frame 1 crc (upper 16 bits). the expected crc value of a wake-up frame 1 pattern. bank 5 wakeup frame 1 byte mask 0 register (0x04): wf1bm0 this register contains the first 16 bytes mask values of the wake up frame 1 pattern. setting bit 0 selects the first byte of the wake up frame 1, setting bit 15 selects the 16th byte of the wake up frame 1. bit default value r/w description 15-0 0 rw wf1bm0 wake-up frame 1 byte mask 0. the first 16 bytes mask of a wake-up frame 1 pattern. bank 5 wakeup frame 1 byte mask 1 register (0x06): wf1bm1 this register contains the next 16 bytes mask values of the wake up frame 1 pattern. setting bit 0 selects the 17th byte of the wake up frame 1. setting bit 15 selects the 32nd byte of the wake up frame 1. bit default value r/w description 15-0 0 rw wf1bm1 wake-up frame 1 byte mask 1. the next 16 bytes mask covering bytes 17 to 32 of a wake-up frame 1 pattern.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 60 m9999-102207-1.6 bank 5 wakeup frame 1 byte mask 2 register (0x08): wf1bm2 this register contains the next 16 bytes mask values of the wake up frame 1 pattern. setting bit 0 selects the 33rd byte of the wake up frame 1. setting bit 15 selects the 48th byte of the wake up frame 1. bit default value r/w description 15-0 0 rw wf1bm2 wake-up frame 1 byte mask 2. the next 16 bytes mask covering bytes 33 to 48 of a wake-up frame 1 pattern. bank 5 wakeup frame 1 byte mask 3 register (0x0a): wf1bm3 this register contains the last 16 bytes mask values of the wake up frame 1 pattern. setting bit 0 selects the 49th byte of the wake up frame 1. setting bit 15 selects the 64th byte of the wake up frame 1. bit default value r/w description 15-0 0 rw wf1bm3 wake-up frame 1 byte mask 3. the last 16 bytes mask covering bytes 49 to 64 of a wake-up frame 1 pattern. bank 6 wakeup frame 2 crc0 register (0x00): wf2crc0 this register contains the expected crc values of the wake up frame 2 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. bit default value r/w description 15-0 0 rw wf2crc0 wake-up frame 2 crc (lower 16 bits). the expected crc value of a wake-up frame 2 pattern. bank 6 wakeup frame 2 crc1 register (0x02): wf2crc1 this register contains the expected crc values of the wake-up frame 2 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. bit default value r/w description 15-0 0 rw wf2crc1 wake-up frame 2 crc (upper 16 bits). the expected crc value of a wake-up frame 2 pattern. bank 6 wakeup frame 2 byte mask 0 register (0x04): wf2bm0 this register contains the first 16 bytes mask values of the wake up frame 2 pattern. setting bit 0 selects the first byte of the wake up frame 2, setting bit 15 selects the 16th byte of the wake up frame 2. bit default value r/w description 15-0 0 rw wf2bm0 wake-up frame 2 byte mask 0. the first 16 bytes mask of a wake-up frame 2 pattern.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 61 m9999-102207-1.6 bank 6 wakeup frame 2 byte mask 1 register (0x06): wf2bm1 this register contains the next 16 bytes mask values of the wake up frame 2 pattern. setting bit 0 selects the 17th byte of the wake up frame 2. setting bit 15 selects the 32nd byte of the wake up frame 2. bit default value r/w description 15-0 0 rw wf2bm1 wake-up frame 2 byte mask 1. the next 16 bytes mask covering bytes 17 to 32 of a wake-up frame 2 pattern. bank 6 wakeup frame 2 byte mask 2 register (0x08): wf2bm2 this register contains the next 16 bytes mask values of the wake up frame 2 pattern. setting bit 0 selects the 33rd byte of the wake up frame 2. setting bit 15 selects the 48th byte of the wake up frame 2. bit default value r/w description 15-0 0 rw wf2bm2 wake-up frame 2 byte mask 2. the next 16 bytes mask covering bytes 33 to 48 of a wake-up frame 2 pattern. bank 6 wakeup frame 2 byte mask 3 register (0x0a): wf2bm3 this register contains the last 16 bytes mask values of the wake up frame 2 pattern. setting bit 0 selects the 49th byte of the wake up frame 2. setting bit 15 selects the 64th byte of the wake up frame 2. bit default value r/w description 15-0 0 rw wf2bm3 wake-up frame 2 byte mask 3. the last 16 bytes mask covering bytes 49 to 64 of a wake-up frame 2 pattern. bank 7 wakeup frame 3 crc0 register (0x00): wf3crc0 this register contains the expected crc values of the wake up frame 3 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard, it is taken over the bytes specified in the wake-up byte mask registers. bit default value r/w description 15-0 0 rw wf3crc0 wake-up frame 3 crc (lower 16 bits). the expected crc value of a wake up frame 3pattern. bank 7 wakeup frame 3 crc1 register (0x02): wf3crc1 this register contains the expected crc values of the wake up frame 3 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard, it is taken over the bytes specified in the wake up byte mask registers. bit default value r/w description 15-0 0 rw wf3crc1 wake-up frame 3 crc (upper 16 bits). the expected crc value of a wake up frame 3 pattern.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 62 m9999-102207-1.6 bank 7 wakeup frame 3 byte mask 0 register (0x04): wf3bm0 this register contains the first 16 bytes mask values of the wake up frame 3 pattern. setting bit 0 selects the first byte of the wake up frame 3, setting bit 15 selects the 16th byte of the wake up frame 3. bit default value r/w description 15-0 0 rw wf3bm0 wake up frame 3 byte mask 0 the first 16 byte mask of a wake up frame 3 pattern. bank 7 wakeup frame 3 byte mask 1 register (0x06): wf3bm1 this register contains the next 16 bytes mask values of the wake up frame 3 pattern. setting bit 0 selects the 17th byte of the wake up frame 3. setting bit 15 selects the 32nd byte of the wake up frame 3. bit default value r/w description 15-0 0 rw wf3bm1 wake up frame 3 byte mask 1 the next 16 bytes mask covering bytes 17 to 32 of a wake up frame 3 pattern. bank 7 wakeup frame 3 byte mask 2 register (0x08): wf3bm2 this register contains the next 16 bytes mask values of the wake up frame 3 pattern. setting bit 0 selects the 33rd byte of the wake up frame 3. setting bit 15 selects the 48th byte of the wake up frame 3. bit default value r/w description 15-0 0 rw wf3bm2 wake up frame 3 byte mask 2 the next 16 bytes mask covering bytes 33 to 48 of a wake up frame 3 pattern. bank 7 wakeup frame 3 byte mask 3 register (0x0a): wf3bm3 this register contains the last 16 bytes mask values of the wake up frame 3 pattern. setting bit 0 selects the 49th byte of the wake up frame 3. setting bit 15 selects the 64th byte of the wake up frame 3. bit default value r/w description 15-0 0 rw wf3bm3 wake up frame 3 byte mask 3. the last 16 bytes mask covering bytes 49 to 64 of a wake up frame 3 pattern. bank 8 ? 15: reserved except bank select register (0xe) .
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 63 m9999-102207-1.6 bank 16 transmit control register (0x00): txcr this register holds control information programmed by the cpu to control the qmu transmit module function. bit default value r/w description 15 - ro reserved. 14-13 0x0 rw reserved. 12-4 - ro reserved. 3 0x0 rw txfce transmit flow control enable when this bit is set and the ksz8841m is in full-duplex mode, flow control is enabled. the ksz8841m transmits a pause frame when the receive buffer capacity reaches a threshold level that will cause the buffer to overflow. when this bit is set and the ksz8841m is in half-duplex mode, back-pressure flow control is enabled. when this bit is cleared, no transmit flow control is enabled. 2 0x0 rw txpe transmit padding enable when this bit is set, the ksz8841m automatically adds a padding field to a packet shorter than 64 bytes. note: setting this bit requires enabling the add crc feature to avoid crc errors for the transmit packet. 1 0x0 rw txce transmit crc enable when this bit is set, the ksz8841m automatically adds a crc checksum field to the end of a transmit frame. 0 0x0 rw txe transmit enable when this bit is set, the transmit module is enabled and placed in a running state. when reset, the transmit process is placed in the stopped state after the transmission of the current frame is completed. bank 16 transmit status register (0x02): txsr this register keeps the status of the last transmitted frame. bit default value r/w description 15 0x0 ro reserved. 14 0x0 ro txur transmit underrun this bit is set when underrun occurs. note: this is a fatal status. software should guarantee that no underrun condition occurred when enabling the early transmit function. the sy stem or the qmu requires a reset or restart to recover from an underrun condition. to aviod transmit underun condition, the user has to make sure that the host interface speed (bandwidth) is faster than the ethernet port. 13 0x0 ro txlc transmit late collision this bit is set when a transmit late collision occurs. 12 0x0 ro txmc transmit maximum collision this bit is set when a transmit maximum collision is reached. 11-6 - ro reserved. 5-0 - ro txfid transmit frame id this field identifies the transmitted frame. all of the transmit status information in this register belongs to the frame with this id.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 64 m9999-102207-1.6 bank 16 receive control register (0x04): rxcr this register holds control information programmed by the cpu to control the receive function. bit default value r/w description 15-11 - ro reserved. 10 0x0 rw rxfce receive flow control enable when this bit is set and the ksz8841m is in full-duplex mode, flow control is enabled, and the ksz8841m will acknowledge a pause frame from the receive interface; i.e., the outgoing packets are pending in the transmit buffer until the pause frame control timer expires. this field has no meaning in half-duplex mode and should be programmed to 0. when this bit is cleared, flow control is not enabled. 9 0x0 rw rxefe receive error frame enable when this bit is set, crc error frames are allowed to be received into the rx queue. when this bit is cleared, all crc error frames are discarded. 8 - ro reserved. 7 0x0 rw rxbe receive broadcast enable when this bit is set, the rx module receives all the broadcast frames. 6 0x0 rw rxme receive multicast enable when this bit is set, the rx module receives all the multicast frames (including broadcast frames). 5 0x0 rw rxue receive unicast when this bit is set, the rx module receives unicast frames that match the 48-bit station mac address of the module. 4 0x0 rw rxra receive all when this bit is set, the ksz8841m receives all incoming frames, regardless of the frame?s destination address. 3 0x0 rw rxsce receive strip crc when this bit is set, the ksz8841m strips the crc on the received frames. once cleared, the crc is stored in memory following the packet. 2 0x0 rw qmu receive multicast hash-table enable when this bit is set, this bit enables the rx function to receive multicast frames that pass the crc hash filtering mechanism. 1 - ro reserved. 0 0x0 rw rxe receive enable when this bit is set, the rx block is enabled and placed in a running state. when this bit is cleared, the receive process is placed in the stopped state upon completing reception of the current frame. bank 16 txq memory information register (0x08): txmir this register indicates the amount of free memory available in the txq of the qmu module. bit default value r/w description 15-13 - ro reserved. 12-0 - ro txma transmit memory available the amount of memory available is represented in units of byte. the txq memory is used for both frame payload, control word. note: software must be written to ensure that there is enough memory for the next transmit frame including control information before transmit data is written to the txq.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 65 m9999-102207-1.6 bank 16 rxq memory information register (0x0a): rxmir this register indicates the amount of receive data available in the rxq of the qmu module. bit default value r/w description 15-13 - ro reserved. 12-0 - ro rxma receive packet data available the amount of receive packet data available is represented in units of byte. the rxq memory is used for both frame payload, status word. there is total 4096 bytes in rxq. this counter will update after a complete packet is received and also issues an interrupt when receive interrupt enable ier[13] in bank 18 is set. note: software must be written to empty the rxq memory to allow for the new rx frame. if this is not done, the frame may be discarded as a result of insufficient rxq memory. bank 17 txq command register (0x00): txqcr this register is programmed by the host cpu to issue a transmit command to the txq. the present transmit frame in the txq memory is queued for transmit. bit default value r/w description 15-1 - ro reserved 0 0x0 rw txetf enqueue tx frame when this bit is written as 1, the current tx frame prepared in the tx buffer is queued for transmit. note: this bit is self-clearing after the frame is finished transmitting. the software should wait for the bit to be cleared before setting up another new tx frame. bank 17 rxq command re gister (0x02): rxqcr this register is programmed by the host cpu to issue release command to the rxq. the current frame in the rxq frame buffer is read only by the host and the memory space is released. bit default value r/w description 15-1 - ro reserved. 0 0x0 rw rxrrf release rx frame when this bit is written as 1, the current rx frame buffer is released. note: this bit is self-clearing after the frame me mory is released. the software should wait for the bit to be cleared before processing new rx frame.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 66 m9999-102207-1.6 bank 17 tx frame data pointer register (0x04): txfdpr the value of this register determines the address to be accessed within the txq frame buffer. when the auto increment is set, it will automatically increment the pointer value on write accesses to the data register. the counter is incremented by one for every byte access, by two for every word access, and by four for every double word access. bit default value r/w description 15 - ro reserved. 14 0x0 rw txfpai tx frame data pointer auto increment when this bit is set, the tx frame data pointer register increments automatically on accesses to the data register. the increment is by one for every byte access, by two for every word access, and by four for every doubleword access. when this bit is reset, the tx frame data pointer is manually controlled by user to access the tx frame location. 13-11 - ro reserved. 10-0 0x000 rw txfp tx frame pointer tx frame pointer index to the frame data register for access. this field reset to next available tx frame location when the tx frame data has been enqueued through the txq command register. bank 17 rx frame data pointer register (0x06): rxfdpr the value of this register determines the address to be accessed within the rxq frame buffer. when the auto increment is set, it will automatically increment the rxq pointer on read accesses to the data register. the counter is incremented is by one for every byte access, by two for every word access, and by four for every double word access. bit default value r/w description 15 - ro reserved. 14 0x0 rw rxfpai rx frame pointer auto increment when this bit is set, the rxq address register increments automatically on accesses to the data register. the increment is by one for every byte access, by two for every word access, and by four for every double word access. when this bit is reset, the rx frame data pointer is manually controlled by user to access the rx frame location. 13-11 - ro reserved. 10-0 0x000 rw rxfp rx frame pointer rx frame data pointer index to the data register for access. this field reset to next available rx frame location when rx frame release command is issued (through the rxq command register).
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 67 m9999-102207-1.6 bank 17 qmu data register low (0x08): qdrl this register qdrl(0x08-0x09) contains the low data word presently addressed by the pointer register. reading maps from the rxq, and writing maps to the txq. bit default value r/w description 15-0 - rw qdrl queue data register low this register is mapped into two uni-directional buffers for 16-bit buses, and one uni-directional buffer for 32-bit buses, (txq when write, rxq when read) that allow moving words to and from the ksz8841m regardless of whether the poi nter is even, odd, or dword aligned. byte, word, and dword access can be mixed on the fly in any order. this register along with dqrh is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit buses, to facilitate dword move operations. bank 17 qmu data regi ster high (0x0a): qdrh this register qdrh(0x0a-0x0b) contains the high data word presently addressed by the pointer register. reading maps from the rxq, and writing maps to the txq. bit default value r/w description 15-0 - rw qdrl queue data register high this register is mapped into two uni-directional buffers for 16-bit buses, and one uni-directional buffer for 32-bit buses, (txq when write, rxq when read) that allow moving words to and from the ksz8841m regardless of whether the poi nter is even, odd, or dword aligned. byte, word, and dword access can be mixed on the fly in any order. this register along with dqrl is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit buses, to facilitate dword move operations.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 68 m9999-102207-1.6 bank 18 interrupt enable register (0x00): ier this register enables the interrupts from the qmu and other sources. bit default value r/w description 15 0x0 rw lcie link change interrupt enable when this bit is set, the link change interrupt is enabled. when this bit is reset, the link change interrupt is disabled. 14 0x0 rw txie transmit interrupt enable when this bit is set, the transmit interrupt is enabled. when this bit is reset, the transmit interrupt is disabled. 13 0x0 rw rxie receive interrupt enable when this bit is set, the receive interrupt is enabled. when this bit is reset, the receive interrupt is disabled. 12 0x0 rw txuie transmit underrun interrupt enable when this bit is set, the transmit underrun interrupt is enabled. when this bit is reset, the transmit underrun interrupt is disabled. 11 0x0 rw rxoie receive overrun interrupt enable when this bit is set, the receive overrun interrupt is enabled. when this bit is reset, the receive overrun interrupt is disabled. 10 0x0 rw rxeie receive early receive interrupt enable when this bit is set, the early receive interrupt is enabled. when this bit is reset, the early receive interrupt is disabled. 9 0x0 rw txpsie transmit process stopped interrupt enable when this bit is set, the transmit process stopped interrupt is enabled. when this bit is reset, the transmit process stopped interrupt is disabled. 8 0x0 rw rxpsie receive process stopped interrupt enable when this bit is set, the receive process stopped interrupt is enabled. when this bit is reset, the receive process stopped interrupt is disabled. 7 0x0 rw rxefie receive error frame interrupt enable when this bit is set, the receive error frame interrupt is enabled. when this bit is reset, the receive error frame interrupt is disabled. 6-0 - ro reserved.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 69 m9999-102207-1.6 bank 18 interrupt status register (0x02): isr this register contains the status bits for all qmu and other interrupt sources. when the corresponding enable bit is set, it causes the interrupt pin to be asserted. this register is usually read by the host cpu and device drivers during interrupt service routine or polling. the register bits are not cleared when read. the user has to write ?1? to clear bit default value r/w description 15 0x0 ro (w1c) lcis link change interrupt status when this bit is set, it indicates that the link status has changed from link up to link down, or link down to link up. this edge-triggered interrupt status is cleared by writing 1 to this bit. 14 0x0 ro (w1c) txis transmit status when this bit is set, it indicates that the txq mac has transmitted at least a frame on the mac interface and the qmu txq is ready for new frames from the host. this edge-triggered interrupt status is cleared by writing 1 to this bit. 13 0x0 ro (w1c) rxis receive interrupt status when this bit is set, it indicates that the qmu rxq has received a frame from the mac interface and the frame is ready for the host cpu to process. this edge-triggered interrupt status is cleared by writing 1 to this bit. 12 0x0 ro (w1c) txuis transmit underrun interrupt status when this bit is set, it indicates that the transmit underrun condition has occurred. this edge-triggered interrupt status is cleared by writing 1 to this bit. 11 0x0 ro (w1c) rxois receive overrun interrupt status when this bit is set, it indicates that the receive overrun status has occurred. this edge-triggered interrupt status is cleared by writing 1 to this bit. 10 0x0 ro (w1c) rxeis receive early receive interrupt status when this bit is set, it indicates that the early receive status has occurred. this edge-triggered interrupt status is cleared by writing 1 to this bit. 9 0x1 ro (w1c) txpsie transmit process stopped status when this bit is set, it indicates that the transmit process has stopped. this edge-triggered interrupt status is cleared by writing 1 to this bit. 8 0x1 ro (w1c) rxpsie receive process stopped status when this bit is set, it indicates that the receive process has stopped. this edge-triggered interrupt status is cleared by writing 1 to this bit. 7 0x0 ro (w1c) rxefie receive error frame interrupt status when this bit is set, it indicates that the receive error frame status has occurred. this edge-triggered interrupt status is cleared by writing 1 to this bit. 6-0 - ro reserved.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 70 m9999-102207-1.6 bank 18 receive status register (0x04): rxsr this register indicates the status of the current received frame and mirrors the receive status word of the receive frame in the rxq. bit default value r/w description 15 - ro rxfv receive frame valid when set, it indicates that the present frame in the receive packet memory is valid. the status information currently in this location is also valid. when clear, it indicates that there is either no pending receive frame or that the current frame is still in the process of receiving. 14-8 - ro reserved. 7 - ro rxbf receive broadcast frame when set, it indicates that this frame has a broadcast address. 6 - ro rxmf receive multicast frame when set, it indicates that this frame has a multicast address (including the broadcast address). 5 - ro rxuf receive unicast frame when set, it indicates that this frame has a unicast address. 4 - ro rxmr receive mii error when set, it indicates that there is an mii symbol error on the received frame. 3 - ro rxft receive frame type when set, it indicates that the frame is an ethernet-type frame (frame length is greater than 1500 bytes). when clear, it indicate that the frame is an ieee 802.3 frame. this bit is not valid for runt frames. 2 - ro rxtl receive frame too long when set, it indicates that the frame length exceeds the maximum size of 1916 bytes. frames that are too long are passed to the host only if the pass bad frame bit is set (bit 9 in rxcr register). note: frame too long is only a frame length indication and does not cause any frame truncation. 1 - ro rxrf receive runt frame when set, it indicates that a frame was damaged by a collision or premature termination before the collision window has passed. runt frames are passed to the host only if the pass bad frame bit is set (bit 9 in rxcr register). 0 - ro rxce receive crc error when set, it indicates that a crc error has occurred on the current received frame. a crc error frame is passed to the host only if the pass bad frame bit is set (bit 9 in rxcr register) bank 18 receive byte count register (0x06): rxbc this register indicates the status of the current received frame and mirrors the receive byte count word of the receive frame in the rxq. bit default value r/w description 15-11 - ro reserved. 10-0 - ro rxbx receive byte count receive byte count.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 71 m9999-102207-1.6 bank 18 early transmit register (0x08): etxr this register specifies the threshold for the early transmit. bit default value r/w description 15-8 - ro reserved. 7 0x0 rw txee early transmit enable when this bit is set, the early transmit function is enabled. when this bit is cleared, normal operation is assumed. 6-5 - ro reserved. 4-0 0x00 rw etxth early transmit threshold the threshold for early transmit. specified in unit of 64-byte. whenever the number of bytes written in memory for the presently transmitting packet exceeds the threshold, early transmit will be started on the network interface. when early transmit is enabled, setting this field to 0 is invalid, and the hardware behavior is unknown. bank 18 early receive register (0x0a): erxr this register specify the threshold for early receive and interrupt condition. bit default value r/w description 15-8 - ro reserved. 7 0x0 rw rxee early receive enable when this bit is set, the early receive function is enabled. when this bit is cleared, normal operation is assumed. 6-5 - ro reserved. 4-0 0x1f rw erxth early receive threshold the threshold for early receive and interrupt. specified in unit of 64-byte. whenever the number of bytes written in memory for the presently received packet exceeds the threshold, early receive status will be set, and early receive interrupt will be asserted if its interrupt is enabled. when early receive is enabled, setting this field to 0 is invalid, and the hardware behavior is unknown. bank 19 multicast table register 0 (0x00): mtr0 the 64-bit multicast table is used for group address filtering. this value is defined as the six most significant bits from crc circuit calculation result that is based on 48-bit of da input. the two most significant bits select one of the four registers to be used, while the others determine which bit within the register. multicast table register 0. bit default value r/w description 15-0 0x0 rw mtr0 multicast table 0 when the appropriate bit is set, if the packet received with da matches the crc, the hashing function is received without being filtered. when the appropriate bit is cleared, the packet will drop. note: when the receive all (rxra) or receive multicast (rxrm) bit is set in the rxcr, all multicast addresses are received regardless of the multicast table value.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 72 m9999-102207-1.6 bank 19 multicast table register 1 (0x02): mtr1 multicast table register 1. bit default value r/w description 15-0 0x0 rw mtr0 multicast table 1 when the appropriate bit is set, if the packet received with da matches the crc, the hashing function is received without being filtered. when the appropriate bit is cleared, the packet will drop. note: when the receive all (rxra) or receive multicast (rxrm) bit is set in the rxcr, all multicast addresses are received regardless of the multicast table value. bank 19 multicast table register 2 (0x04): mtr2 multicast table register 2. bit default value r/w description 15-0 0x0 rw mtr0 multicast table 2 when the appropriate bit is set, if the packet received with da matches the crc, the hashing function is received without being filtered. when the appropriate bit is cleared, the packet will drop. note: when the receive all (rxra) or receive multicast (rxrm) bit is set in the rxcr, all multicast addresses are received regardless of the multicast table value. bank 19 multicast table register 3 (0x06): mtr3 multicast table register 3. bit default value r/w description 15-0 0x0 rw mtr0 multicast table 3 when the appropriate bit is set, if the packet received with da matches the crc, the hashing function is received without being filtered. when the appropriate bit is cleared, the packet will drop. note: when the receive all (rxra) or receive multicast (rxrm) bit is set in the rxcr, all multicast addresses are received regardless of the multicast table value. bank 19 power management control and status register (0x08): pmcs the following control and status register provides information on the ksz8841m power management capabilities. the following table shows the register bit fields. bit default value r/w description 15 0 ro (w1c) pme_status this bit indicates that the ksz8841m has detected a power-management event. if bit pme_enable is set, the ksz8841m also asserts the pmen pin. this bit is cleared on power- up reset or by write 1. it is not modified by either hardware or software reset. when this bit is cleared, the ksz8841m deasserts the pmen pin. 14-9 0x00 ro reserved. 8 0 rw pme_enable if this bit is set, the ksz8841m can assert the pmen pin. otherwise, assertion of the pmen pin is disabled. this bit is cleared on power-up reset and will be not modified by software reset. 7-4 0x0 ro reserved.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 73 m9999-102207-1.6 bit default value r/w description 3 0 ro no soft reset if this bit is set (?1?), the ksz8841m does not perform an internal reset when transitioning from d3_hot to d0 because of powerstate commands. configuration context is preserved. upon transition from d3_hot to the d0 initialized state, no additional operating system intervention is required to preserve configuration context beyond writing the powerstate bits. if this bit is cleared (?0?), the ksz8841m does perform an internal reset when transitioning from d3_hot to d0 via software control of the powerstate bits. configuration context is lost when performing the soft reset. upon transition from d3_hot to the d0 state, full reinitialization sequence is needed to return the device to d0 initialized. regardless of this bit, devices that transition from d3_hot to d0 by a system or bus segment reset will return to the device state d0 uninitialized with only pme context preserved if pme is supported and enabled. the value of this bit is loaded from the no_srst bit in the serial eeprom. 2 0 ro reserved. 1-0 0x0 rw power state this field is used to set the new power state of the ksz8841m as well as to determine its current power state. the definitions of the field values are: 00: d0 -> system is on and running 01: d1 -> low-power state 10: d2 -> low-power state 11: d3 (hot) -> system is off and not running banks 20 ? 31: reserved except bank select register (0xe). bank 32 chip id and enab le register (0x00): cider this register contains the chip id and the chip enable bit. bit default r/w description 15-8 0x88 ro family id chip family id 7-4 0x1 ro chip id 0x1 is assigned to ksz8841m 3-1 0x1 ro revision id 0 0 ro reserved.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 74 m9999-102207-1.6 bank 32 chip global control register (0x0a): cgcr this register contains the global control for the chip function. bit default r/w description 15 0 rw ledsel1 see description for bit 9. 14-12 0 rw reserved. 11-10 0x2 rw reserved. 9 0 rw ledsel0 this register bit sets the ledsel0 selection only. port 1 led indicators, defined as below: [ledsel1, ledsel0] [0, 0] [0, 1] p1led3 ------ ------ p1led2 link/act 100link/act p1led1 full_dpx/col 10link/act p1led0 speed full_dpx [ledsel1, ledsel0] [1, 0] [1, 1] p1led3 act ------ p1led2 link ------ p1led1 full_dpx/col ------ p1led0 speed ------ 8 0 r/w reserved. 7-0 0x35 rw reserved. banks 33 ? 41: reserved except bank select register (0xe)
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 75 m9999-102207-1.6 bank 42 indirect access control register (0x00): iacr this register contains the indirect control for the mib counter (write iacr triggers a command. read or write access is determined by register bit 12). bit default r/w description 15-13 0x0 rw reserved. 12 0 rw read high. write low 1 = read cycle. 0 = write cycle. 11-10 0x0 rw table select 00 = reserved. 01 = reserved. 10 = reserved. 11 = mib counter selected. 9-0 0x000 rw indirect address bit 9-0 of indirect address. bank 42 indirect access data register 1 (0x02): iadr1 this register contains the indirect data for the chip function. bit default r/w description 15-0 0x0000 ro reserved. bank 42 indirect access data register 2 (0x04): iadr2 this register contains the indirect data for the chip function. bit default r/w description 15-0 0x0000 ro reserved. bank 42 indirect access data register 3 (0x06): iadr3 this register contains the indirect data for the chip function. bit default r/w description 15-0 0x0000 ro reserved. bank 42 indirect access data register 4 (0x08): iadr4 this register contains the indirect data for the chip function. bit default r/w description 15-0 0x0000 rw indirect data bit 15-0 of indirect data. bank 42 indirect access data register 5 (0x0a): iadr5 this register contains the indirect data for the chip function. bit default r/w description 15-0 0x0000 rw indirect data bit 31-16 of indirect data. bank 43? 44: reserved except bank select register (0xe)
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 76 m9999-102207-1.6 bank 45 phy 1 mii-register basi c control register (0x00): p1mbcr this register contains media independent interface (mii) register for port 1 as defined in the ieee 802.3 specification. bit default r/w description bit is same as: 15 0 ro soft reset not supported. 14 0 rw reserved. 13 0 rw force 100 1 = force 100mbps if an is disabled (bit 12) 0 = force 10mbps if an is disabled (bit 12) bank49 0x2 bit6 12 1 rw an enable 1 = auto-negotiation enabled. 0 = auto-negotiation disabled. bank49 0x2 bit7 11 0 rw power-down 1 = power-down. 0 = normal operation. bank49 0x2 bit11 10 0 ro isolate not supported. 9 0 rw restart an 1 = restart auto-negotiation. 0 = normal operation. bank49 0x2 bit13 8 0 rw force full duplex 1 = force full duplex 0 = force half duplex. if an is disabled (bit 12) or an is enabled but failed. bank49 0x2 bit5 7 0 ro collision test not supported. 6 0 ro reserved. 5 1 r/w hp_mdix 1 = hp auto mdi-x mode. 0 = micrel auto mdi-x mode. bank49 0x4 bit15 4 0 rw force mdi-x 1 = force mdi-x. 0 = normal operation. bank49 0x2 bit9 3 0 rw disable mdi-x 1 = disable auto mdi-x. 0 = normal operation. bank49 0x2 bit10 2 0 rw reserved. bank49 0x2 bit12 1 0 rw disable transmit 1 = disable transmit. 0 = normal operation. bank49 0x2 bit14 0 0 rw disable led 1 = disable led. 0 = normal operation. bank49 0x2 bit15
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 77 m9999-102207-1.6 bank 45 phy 1 mii-register basic status register (0x02): p1mbsr this register contains the mii register status for the chip function. bit default r/w description bit is same as: 15 0 ro t4 capable 1 = 100 base-t4 capable. 0 = not 100 base-t4 capable. 14 1 ro 100 full capable 1 = 100base-tx full-duplex capable. 0 = not 100base-tx full duplex.capable. 13 1 ro 100 half capable 1= 100base-tx half-duplex capable. 0= not 100base-tx half-duplex capable. 12 1 ro 10 full capable 1 = 10base-t full-duplex capable. 0 = not 10base-t full-duplex capable. 11 1 ro 10 half capable 1 = 10base-t half-duplex capable. 0 = not 10base-t half-duplex capable. 10-7 0 ro reserved . 6 0 ro preamble suppressed not supported. 5 0 ro an complete 1 = auto-negotiation complete. 0 = auto-negotiation not completed. bank49 0x4 bit6 4 0 ro reserved bank49 0x4 bit8 3 1 ro an capable 1 = auto-negotiation capable. 0 = not auto-negotiation capable. 2 0 ro link status 1 = link is up. 0 = link is down. bank49 0x4 bit5 1 0 ro jabber test not supported. 0 0 ro extended capable 1 = extended register capable. 0 = not extended register capable. bank 45 phy 1 phyid low register (0x04): phy1ilr this register contains the phy id (low) for the chip. bit default r/w description 15-0 0x1430 ro phyid low low order phyid bits.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 78 m9999-102207-1.6 bank 45 phy 1 phyid high register (0x06): phy1ihr this register contains the phy id (high) for the chip. bit default r/w description 15-0 0x0022 ro phyid high high order phyid bits. bank 45 phy 1 auto-negotiation advertisement register (0x08): p1anar this register contains the auto-negotiation advertisement for the phy function. bit default r/w description bit is same as: 15 0 ro next page not supported. 14 0 ro reserved 13 0 ro remote fault not supported. 12-11 0 ro reserved 10 1 rw pause (flow control capability) 1 = advertise pause capability. 0 = do not advertise pause capability. bank49 0x2 bit4 9 0 rw reserved. 8 1 rw adv 100 full 1 = advertise 100 full-duplex capability. 0 = do not advertise 100 full-duplex capability bank49 0x2 bit3 7 1 rw adv 100 half 1= advertise 100 half-duplex capability. 0 = do not advertise 100 half-duplex capability. bank49 0x2 bit2 6 1 rw adv 10 full 1 = advertise 10 full-duplex capability. 0 = do not advertise 10 full-duplex capability. bank49 0x2 bit1 5 1 rw adv 10 half 1 = advertise 10 half-duplex capability. 0 = do not advertise 10 half-duplex capability. bank49 0x2 bit0 4-0 0x01 ro selector field 802.3 bank 45 phy 1 auto-negotiation link partner ability register (0x0a): p1anlpr this register contains the auto-negotiation link partner ability for the chip function. bit default r/w description bit is same as: 15 0 ro next page not supported. 14 0 ro lp ack not supported. 13 0 ro remote fault not supported. 12-11 0 ro reserved
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 79 m9999-102207-1.6 bit default r/w description bit is same as: 10 0 ro pause link partner pause capability. bank49 0x4 bit4 9 0 ro reserved. 8 0 ro adv 100 full link partner 100 full capability. bank49 0x4 bit3 7 0 ro adv 100 half link partner 100 half capability. bank49 0x4 bit2 6 0 ro adv 10 full link partner 10 full capability. bank49 0x4 bit1 5 0 ro adv 10 half link partner 10 half capability. bank49 0x4 bit0 4-0 0x01 ro reserved. bank 46: reserved except bank select register (0xe) bank 47 phy1 linkmd control/status (0x00): p1vct this register contains the linkmd control and status information of phy 1. bit default r/w description bit is same as: 15 0 rw (self- clear) vct_enable 1 = cable diagnostic test is enabled. it is self-cleared after the vct test is done. 0 = indicates that the cable diagnostic test is completed and the status information is valid for read. bank49 0x0 bit 12 14-13 0 ro vct_result [00] = normal condition. [01] = open condition detected in the cable. [10] = short condition detected in the cable. [11] = cable diagnostic test failed. bank49 0x0 bit 14-13 12 - ro vct 10m short 1 = less than 10m short. bank49 0x0 bit 15 11-9 0x0 ro reserved. 8-0 0x000 ro vct_fault_count distance to the fault. the distance is approximately 0.4m*vct_fault_count. bank49 0x0 bit 8-0
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 80 m9999-102207-1.6 bank 47 phy1 special control/status register (0x02): p1phyctrl this register contains the control and status information of phy1. bit default r/w description bit is same as: 15-6 0x000 ro reserved. 5 0 ro polarity reverse (polrvs) 1 = polarity is reversed. 0 = polarity is not reversed. bank49 0x04 bit13 4 0 ro mdix status (mdix_st) 1 = mdi 0 = mdix bank49 0x04 bit7 3 0 rw force link (force_lnk) 1 = force link pass. 0 = normal operation. bank49 0x00 bit11 2 1 rw power saving (pwrsave) 1 = disable power saving. 0 = enable power saving. bank49 0x00 bit10 1 0 rw remote (near-end) loopback (rlb) 1 = perform remote loopback at phy (rxp1/rxm1 -> txp1/txm1, see figure 12) 0 = normal operation bank49 0x00 bit9 0 0 rw reserved. bank 48: reserved except bank select register (0xe)
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 81 m9999-102207-1.6 bank 49 port 1 phy special control/status, linkmd (0x00): p1scslmd bit default r/w description is same as: 15 0 ro vct_10m_short 1 = less than 10 meter short. bank 47 0x00 bit 12 14-13 0 ro vct_result vct result. [00] = normal condition. [01] = open condition has been detected in cable. [10] = short condition has been detected in cable. [11] = cable diagnostic test is failed. bank 47 0x00 bit 14-13 12 0 rw (self- clear) vct_en vct enable. 1 = the cable diagnostic test is enabled. it is self- cleared after the vct test is done. 0 = it indicates the cable diagnostic test is completed and the status information is valid for read. bank 47 0x00 bit 15 11 0 rw force_lnk force link. 1 = force link pass. 0 = normal operation. bank 47 0x02 bit 3 10 1 rw pwrsave power-saving. 1 = disable power saving. 0 = enable power saving. bank 47 0x02 bit 2 9 0 rw remote (near-end) loopback (rlb) 1 = perform remote loopback at phy (rxp1/rxm1 -> txp1/txm1, see figure 12) 0 = normal operation bank 47 0x02 bit 1 8-0 0x000 ro vct_fault_count vct fault count. distance to the fault. it?s approximately 0.4m*vct_fault_count. bank 47 0x00 bit 8-0
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 82 m9999-102207-1.6 bank 49 port 1 control register 4 (0x02): p1cr4 this register contains the global per port control for the chip function. bit default r/w description bit is same as: 15 0 rw led off 1 = turn off all of the port 1 leds (p1led3, p1led2, p1led1, p1led0). these pins are driven high if this bit is set to one. 0 = normal operation. bank 45 0x00 bit 0 14 0 rw txids 1 = disable the port?s transmitter. 0 = normal operation. bank45 0x00 bit 1 13 0 rw restart an 1 = restart auto-negotiation. 0 = normal operation. bank 45 0x00 bit 9 12 0 rw reserved bank 45 0x00 bit 2 11 0 rw power down 1 = power down. 0 = normal operation. bank 45 0x00 bit 11 10 0 rw disable auto mdi/mdi-x 1 = disable auto mdi/mdi-x function. 0 = enable auto mdi/mdi-x function. bank 45 0x00 bit 3 9 0 rw force mdi-x 1= if auto mdi/mdi-x is disabled, force phy into mdi-x mode. 0 = do not force phy into mdi-x mode. bank 45 0x00 bit 4 8 0 rw reserved 7 1 rw auto negotiation enable 1 = auto negotiation is enabled. 0 = disable auto negotiation, speed, and duplex are decided by bits 6 and 5 of the same register. bank 45 0x00 bit 12 6 0 rw force speed 1 = force 100bt if an is disabled (bit 7). 0 = force 10bt if an is disabled (bit 7). bank 45 0x00 bit 13 5 0 rw force duplex 1 = force full duplex if (1) an is disabled or (2) an is enabled but failed. 0 = force half duplex if (1) an is disabled or (2) an is enabled but failed. bank 45 0x00 bit 8 4 1 rw advertised flow control capability. 1 = advertise flow control (pause) capability. 0 = suppress flow control (pause) capability from transmission to link partner. bank 45 0x08 bit 10 3 1 rw advertised 100bt full-duplex capability. 1 = advertise 100bt full-duplex capability. 0 = suppress 100bt full-duplex capability from transmission to link partner. bank 45 0x08 bit 8
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 83 m9999-102207-1.6 bit default r/w description bit is same as: 2 1 rw advertised 100bt half-duplex capability. 1 = advertise 100bt half-duplex capability. 0 = suppress 100bt half-duplex capability from transmission to link partner. bank 45 0x08 bit 7 1 1 rw advertised 10bt full-duplex capability. 1 = advertise 10bt full-duplex capability. 0 = suppress 10bt full-duplex capability from transmission to link partner. bank 45 0x08 bit 6 0 1 rw advertised 10bt half-duplex capability. 1 = advertise 10bt half-duplex capability. 0 = suppress 10bt half-duplex capability from transmission to link partner. bank 45 0x08 bit 5 bank 49 port 1 status register (0x04): p1sr this register contains the global per port status for the chip function. bit default r/w description bit is same as: 15 1 rw hp_mdix 1 = hp auto mdi-x mode. 0 = micrel auto mdi-x mode. bank 45 0x00 bit 5 14 0 ro reserved 13 0 ro polarity reverse 1 = polarity is reversed. 0 = polarity is not reversed. bank 47 0x02 bit 5 12 0 ro receive flow control enable 1 = receive flow control feature is active. 0 = receive flow control feature is inactive. 11 0 ro transmit flow control enable 1 = transmit flow control feature is active. 0 = transmit flow control feature is inactive. 10 0 ro operation speed 1 = link speed is 100mbps. 0 = link speed is 10mbps. 9 0 ro operation duplex 1 = link duplex is full. 0 = link duplex is half. 8 0 ro reserved bank 45 0x02 bit 4 7 0 ro mdi-x status 1 = mdi. 0 = mdi-x. bank 47 0x02 bit 4 6 0 ro an done 1 = an done. 0 = an not done. bank 45 0x02 bit 5 5 0 ro link good 1= link good. bank 45 0x02 bit 2
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 84 m9999-102207-1.6 bit default r/w description bit is same as: 0 = link not good. 4 0 ro partner flow control capability. 1 = link partner flow control (pause) capable. 0 = link partner not flow control (pause) capable. bank 45 0x0a bit 10 3 0 ro partner 100bt full-duplex capability. 1 = link partner 100bt full-duplex capable. 0 = link partner not 100bt full-duplex capable. bank 45 0x0a bit 8 2 0 ro partner 100bt half-duplex capability. 1 = link partner 100bt half-duplex capable. 0= link partner not 100bt half-duplex capable. bank 45 0x0a bit 7 1 0 ro partner 10bt full-duplex capability. 1= link partner 10bt full-duplex capable. 0 = link partner not 10bt full-duplex capable. bank 45 0x0a bit 6 0 0 ro partner 10bt half-duplex capability. 1 = link partner 10bt half-duplex capable. 0 = link partner not 10bt half-duplex capable. bank 45 0x0a bit 5 banks 50 ? 63: reserved except bank select register (0xe)
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 85 m9999-102207-1.6 mib (management information base) counters the ksz8841m provides 32 mib counters to monitor the port activity for network management. the mib counters are formatted as shown below. bit name r/w description default 31 overflow ro 1 = counter overflow. 0 = no counter overflow. 0 30 count valid ro 1 = counter value is valid. 0 = 0 counter value is not valid. 0 29-0 counter values ro counter value (read clear) 0x00000000 table 11. format of mib counters ethernet port mib counters are read using indirect memory access. the address offset range is 0x00 to 0x1f. offset counter name description 0x0 rxloprioritybyte rx lo-priority (default) octet count including bad packets 0x1 reserved reserved. 0x2 rxundersizepkt rx undersize packets w/ good crc 0x3 rxfragments rx fragment packets w/ bad crc, symbol errors or alignment errors 0x4 rxoversize rx oversize packets w/ good crc (max: 1536 bytes) 0x5 rxjabbers rx packets longer than 1536 bytes w/ either crc errors, alignment errors, or symbol errors 0x6 rxsymbolerror rx packets w/ invalid data symbol and legal packet size. 0x7 rxcrcerror rx packets within (64,1916) bytes w/ an integral number of bytes and a bad crc 0x8 rxalignmenterror rx packets within (64,1916) bytes w/ a non-integral number of bytes and a bad crc 0x9 rxcontrol8808pkts number of mac control frames received by a port with 88-08h in ethertype field 0xa rxpausepkts number of pause frames received by a port. pause frame is qualified with ethertype (88- 08h), da, control opcode (00-01), data length (64b min), and a valid crc 0xb rxbroadcast rx good broadcast packets (not including error broadcast packets or valid multicast packets) 0xc rxmulticast rx good multicast packets (not including mac control frames, error multicast packets or valid broadcast packets) 0xd rxunicast rx good unicast packets 0xe rx64octets total rx packets (bad packets included) that were 64 octets in length 0xf rx65to127octets total rx packets (bad packets included) that are between 65 and 127 octets in length 0x10 rx128to255octets total rx packets (bad packets included) that are between 128 and 255 octets in length 0x11 rx256to511octets total rx packets (bad packets included) that are between 256 and 511 octets in length 0x12 rx512to1023octets total rx packets (bad packets included) that are between 512 and 1023 octets in length 0x13 rx1024to1522octets total rx packets (bad packets included) that are between 1024 and 1916 octets in length 0x14 txloprioritybyte tx lo-priority good octet count, including pause packets 0x15 reserved reserved. 0x16 txlatecollision the number of times a collision is detected later than 512 bit-times into the tx of a packet 0x17 txpausepkts number of pause frames transmitted by a port 0x18 txbroadcastpkts tx good broadcast packets (not incl uding error broadcast or valid multicast packets)
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 86 m9999-102207-1.6 offset counter name description 0x19 txmulticastpkts tx good multicast packets (not including error multicast packets or valid broadcast packets) 0x1a txunicastpkts tx good unicast packets 0x1b txdeferred tx packets by a port for which the 1st tx attempt is delayed due to the busy medium 0x1c txtotalcollision tx total collision, half duplex only 0x1d txexcessivecollision a count of frames for which tx fails due to excessive collisions 0x1e txsinglecollision successfully tx frames on a po rt for which tx is inhibited by exactly one collision 0x1f txmultiplecollision successfully tx frames on a port for which tx is inhibited by more than one collision table 12. port 1 mib counters indirect memory offsets example: 1. mib counter read (read port 1 ?rx64octets? counter at indirect address offset 0x0e) write to reg. iacr with 0x1c0e (set indirect address and trigger a read mib counters operation) then read reg. iadr5 (mib counter value 31-16) // if bit 31 = 1, there was a counter overflow // if bit 30 = 0, restart (re-read) from this register read reg. iadr4 (mib counter value 15-0) additional mib information in the heaviest condition, the byte counter will overflow in 2 minutes. it is recommended that the software read all the counters at least every 30 seconds. mib counters are designed as ?read clear?. that is, these counters will be cleared after they are read.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 87 m9999-102207-1.6 absolute maximum ratings (1) description pins value supply voltage vddatx, vddarx, vddio ?0.5v to +4.0v input voltage all inputs ?0.5v to +5v output voltage all outputs ?0.5v to +4.0v lead temperature (soldering, 10 sec) n/a 270 c storage temperature (t s ) n/a ?55 c to +150 c table 13. maximum ratings note: exceeding the absolute maximum rating may damage the device. st resses greater than those listed in the table above may cause permanent damage to the device. operation of the device at these or any other conditi ons above those specified in the operating sections of this specification is not implied. maximum condition s for extended periods may affect reliability. unused inputs mu st always be tied to an appropriate logic voltage level. operating ratings (1) parameter symbol min typ max supply voltages vddatx,vddarx vddio 3.1v 3.1v 3.3v 3.3v 3.5v 3.5v ambient temperature for commercial t a 0 c +70c ambient temperature for industrial t a -40 c +85c maximum junction temperature t j +125c thermal resistance junction-to-ambient (2) ja 42.91 c/w thermal resistance junction-to-case (2) jc 19.6 c/w table 14. operating ratings notes: 1. the device is not guaranteed to function outside its operating rating. unused inputs mu st always be tied to an appropriate l ogic voltage level (ground to v dd ). 2. no (hs) heat spreader in this package. the jc / ja is under air velocity 0 m/s.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 88 m9999-102207-1.6 electrical characteristics (1) parameter symbol condition min typ max supply current for 100base-tx operation (single port@100% utilization) 100base-tx (analog core + pll + digital core + transceiver + digital i/o) i ddxio vddatx, vddarx, vddio = 3.3v; chip only (no transformer) 100 ma supply current for 10base-t operation ( single port@100% utilization) 10base-t (analog core + pll + digital core + transceiver + digital i/o) i ddxio vddatx, vddarx, vddio = 3.3v; chip only (no transformer) 85 ma ttl inputs input high voltage v ih 2.0v input low voltage v il 0.8v input current i in v in = gnd ~ vddio -10 a 10 a ttl outputs output high voltage v oh i oh = -8 ma 2.4v output low voltage v ol i ol = 8 ma 0.4v output tri-state leakage |i oz | 10 a 100basetx transmit (measured differentially after 1:1 transformer) peak differential output voltage v o 100 ? termination on the differential output. + 0.95v + 1.05v output voltage imbalance v imb 100 ? termination on the differential output 2% rise/fall time t r /t f 3ns 5ns rise/fall time imbalance 0ns 0.5ns duty cycle distortion + 0.25ns overshoot 5% reference voltage of iset v set 0.5v output jitter peak-to-peak 0.7ns 1.4ns 10baset receive squelch threshold v sq 5mhz square wave. 400mv 10baset transmit (measured differentially after 1:1 transformer) peak differential output voltage v p 100 ? termination on the differential output. 2.4v jitter added 100 ? termination on the differential output.( peak-to-peak) 1.8ns 3.5ns table 15. electrical characteristics notes: 1. ta = 25c. specification for packaged product only. 2. single port?s transformer consumes an additional 45ma @3.3v for 100base-tx and 70ma @3.3v for 10base-t.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 89 m9999-102207-1.6 timing specifications asynchronous timing without using address strobe (adsn = 0) figure 13. asynchronous cycle ? adsn = 0 symbol parameter min typ max unit t1 a1-a15, aen, bexn[3:0] valid to rdn, wrn active 0 ns a1-a15, aen, bexn[3:0] hold after rdn inactive (assume adsn tied low) 0 ns t2 a1-a15, aen, bexn[3:0] hold after wrn inactive (assume adsn tied low) 1 ns t3 read data valid to ardy rising 0.8 ns t4 read data to hold rdn inactive 4 ns t5 write data setup to wrn inactive 4 ns t6 write data hold after wrn inactive 2 ns t7 read active to ardy low 8 ns t8 write inactive to ardy low 8 ns ardy low (wait time) in read cycle (note1) (it is 0ns to read bank select register and 40ns to read qmu data register in turbo mode) (note2) 0 40 ns t9 ardy low (wait time) in read cycle (note1) (it is 0ns to read bank select register and 80ns to read qmu data register in normal mode) 0 80 ns t10 ardy low (wait time) in write cycle (note1) (it is 0ns to write bank select register) (it is 36ns to write qmu data register) 0 50 ns table 16. asynchronous cycle (adsn = 0) timing parameters notes: 1. when cpu finished current read or write operation, it can do next read or write operation even the ardy is low. during read or write operation if the adry is low, the cpu has to keep the rdn/wrn low until the ardy returns to high. 2. in order to speed up the ardy low time to 40 ns, user has to us e the turbo software driver which is only supported in the a6 devi ce. please refer to the ?ksz88xx programmer's guide? for detail. t6 t5 t1 t4 t3 t2 valid valid valid addr, aen, bexn adsn read data rdn, wrn write data t7 ardy (read cycle) ardy ( write cycle) t 8 t9 t1 0
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 90 m9999-102207-1.6 asynchronous timing using address strobe (adsn) t2 t7 t5 t4 t3 t1 t6 t8 valid valid valid a ddr, aen, bexn a dsn read data rdn, wrn write data a rdy (read cycle) a rdy ( write cycle) t 9 t10 t11 figure 14. asynchronous cycle ? using adsn symbol parameter min typ max unit t1 a1-a15, aen, bexn[3:0] valid to rdn, wrn active 0 ns t2 read data valid to ardy rising 0.8 ns t3 read data hold to rdn inactive 4 ns t4 write data setup to wrn inactive 4 ns t5 write data hold after wrn inactive 2 ns t6 a1-a15, aen, nbe[3:0] setup to adsn rising 4 ns t7 read active to ardy low 8 ns t8 a1-a15, aen, bexn[3:0] hold after adsn rising 2 ns t9 write inactive to ardy low 8 ns ardy low (wait time) in read cycle (note1) (it is 0ns to read bank select register and 40ns to read qmu data register in turbo mode) (note2) 0 40 ns t10 ardy low (wait time) in read cycle (note1) (it is 0ns to read bank select register and 80ns to read qmu data register in normal mode) 0 80 ns t11 ardy low (wait time) in write cycle (note1) (it is 0ns to write bank select register) (it is 36ns to write qmu data register) 0 50 ns table 17. asynchronous cycle using adsn timing parameters notes: 1. when cpu finished current read or write operation, it can do next read or write operation even the ardy is low. during read or write operation if the adry is low, the cpu has to keep the rdn/wrn low until the ardy returns to high. 2. in order to speed up the ardy low time to 40ns, user has to use the turbo software driver which is only supported in the a6 device. please refer to the ?ksz88xx programmer's guide? for detail.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 91 m9999-102207-1.6 asynchronous timing using datacsn t3 t7 t6 t5 t4 t1 t2 valid valid datacsn read data rdn, wrn write data a rdy (read cycle) a rdy ( write cycle) t 8 t9 t10 figure 15. asynchronous cycle ? using datacsn symbol parameter min typ max unit t1 datacsn setup to rdn, wrn active 2 ns t2 datacsn hold after rdn, wrn inactive (assume adsn tied low) 0 ns t3 read data hold to ardy rising 0.8 ns t4 read data to rdn hold 4 ns t5 write data setup to wrn inactive 4 ns t6 write data hold after wrn inactive 2 ns t7 read active to ardy low 8 ns t8 write inactive to ardy low 8 ns ardy low (wait time) in read cycle (note1) (it is 0ns to read bank select register and 40ns to read qmu data register in turbo mode) (note2) 0 40 ns t9 ardy low (wait time) in read cycle (note1) (it is 0ns to read bank select register and 80ns to read qmu data register in normal mode) 0 80 ns t10 ardy low (wait time) in write cycle (note1) (it is 0ns to write bank select register) (it is 36ns to write qmu data register) 0 50 ns table 18. asynchronous cycle using datacsn timing parameters notes: 1. when cpu finished current read or write operation, it can do next read or write operation even the ardy is low. during read or write operation if the adry is low, the cpu has to keep the rdn/wrn low until the ardy returns to high. 2. in order to speed up the ardy low time to 40 ns, user has to use the turbo software driver which is only supported in the a6 device. please refer to the ?ksz 88xx programmer's gu ide? for detail.
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 92 m9999-102207-1.6 address latching timing for all modes t3 t2 t1 ad sn address, aen, bexn ldevn figure 16. address latching cycle for all modes symbol parameter min typ max unit t1 a1-a15, aen, bexn[3:0] setup to adsn 4 ns t2 a1-a15, aen, bexn[3:0] hold after adsn rising 2 ns t3 a4-a15, aen to ldevn delay 5 ns table 19. address latching timing parameters
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 93 m9999-102207-1.6 synchronous timing in burst write (vlbusn = 1) figure 17. synchronous burst write cycles ? vlbusn = 1 symbol parameter min typ max unit t1 swr setup to bclk falling 4 ns t2 datdcsn setup to bclk rising 4 ns t3 cyclen setup to bclk rising 4 ns t4 write data setup to bclk rising 6 ns t5 write data hold to bclk rising 2 ns t6 rdyrtnn setup to bclk falling 5 ns t7 rdyrtnn hold to bclk falling 3 ns t8 srdyn setup to bclk rising 4 ns t9 srdyn hold to bclk rising 3 ns t10 datacsn hold to bclk rising 2 ns t11 swr hold to bclk falling 2 ns t12 cyclen hold to bclk 2 ns table 20. synchronous burst write timing parameters
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 94 m9999-102207-1.6 synchronous timing in burst read (vlbusn = 1) t9 t8 t7 t6 t5 t4 t3 t1 t2 data0 data1 data2 data3 bclk datacsn swr cyclen read data rdyrtnn srdyn t11 t10 t12 figure 18. synchronous burst read cycles ? vlbusn = 1 symbol parameter min typ max unit t1 swr setup to bclk falling 4 ns t2 datdcsn setup to bclk rising 4 ns t3 cyclen setup to bclk rising 4 ns t4 read data setup to bclk rising 6 ns t5 read data hold to bclk rising 2 ns t6 rdyrtnn setup to bclk falling 5 ns t7 rdyrtnn hold to bclk falling 3 ns t8 srdyn setup to bclk rising 4 ns t9 srdyn hold to bclk rising 3 ns t10 datacsn hold to bclk rising 2 ns t11 swr hold to bclk falling 2 ns t12 cyclen hold to bclk 2 ns table 21. synchronous burst read timing parameters
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 95 m9999-102207-1.6 synchronous write timing (vlbusn = 0) t12 t11 t10 t9 t8 t7 t4 t3 t6 t5 t1 t2 valid valid bclk ad d re s s , aen , bexn ad sn swr cyclen write data srdyn rdyrtnn figure 19. synchronous write cycle ? vlbusn = 0 symbol parameter min typ max unit t1 a1-a15, aen, bexn[3:0] setup to adsn rising 4 ns t2 a1-a15, aen, bexn[3:0] hold after adsn rising 2 ns t3 cyclen setup to bclk rising 4 ns t4 cyclen hold after bclk rising (non-burst mode) 2 ns t5 swr setup to bclk 4 ns t6 swr hold after bclk rising with srdyn active 0 ns t7 write data setup to bclk rising 5 ns t8 write data hold from bclk rising 1 ns t9 srdyn setup to bclk 8 ns t10 srdyn hold to bclk 1 ns t11 rdyrtnn setup to bclk 4 ns t12 rdyrtnn hold to bclk 1 ns table 22. synchronous write (vlbusn = 0) timing parameters
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 96 m9999-102207-1.6 synchronous read timing (vlbusn = 0) t11 t10 t9 t8 t6 t7 t4 t3 t5 t1 t2 valid valid bclk ad d re s s , aen , bexn ad sn swr cyclen read data srdyn rdyrtnn figure 20. synchronous read cycle ? vlbusn = 0 symbol parameter min typ max unit t1 a1-a15, aen, bexn[3:0] setup to adsn rising 4 ns t2 a1-a15, aen, bexn[3:0] hold after adsn rising 2 ns t3 cyclen setup to bclk rising 4 ns t4 cyclen hold after bclk rising (non-burst mode) 2 ns t5 swr setup to bclk 4 ns t6 read data hold from bclk rising 1 ns t7 read data setup to bclk 8 ns t8 srdyn setup to bclk 8 ns t9 srdyn hold to bclk 1 ns t10 rdyrtnn setup to bclk rising 4 ns t11 rdyrtnn hold after bclk rising 1 ns table 23. synchronous read (vlbusn = 0) timing parameters
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 97 m9999-102207-1.6 auto negotiation timing figure 21. auto negotiation timing timing parameter description min typ max unit t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulses per burst 17 33 table 24. auto negotiation timing parameters
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 98 m9999-102207-1.6 reset timing as long as the stable supply voltages to reset high timing (minimum of 10ms) are met, there is no power-sequencing requirement for the ksz8841m supply voltages (3.3v). the reset timing requirement is summarized in the figure 22 and table 25. supply voltage rst_n tsr figure 22. reset timing symbol parameter min max unit t sr stable supply voltages to reset high 10 ms table 25. reset timing parameters
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 99 m9999-102207-1.6 eeprom timing eesk eecs eedi eedo high-z d15 d14 d13 d1 d0 an a0 0 11 1 *1 *1 start bit tcyc ts th figure 23. eeprom read cycle timing diagram timing parameter description min typ max unit tcyc clock cycle 4 (obcr[1:0]=11 on-chip bus speed @ 25 mhz) or 0.8 (obcr[1:0]=00 on-chip bus speed @ 125 mhz) s ts setup time 20 ns th hold time 20 ns table 26. eeprom timing parameters
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 100 m9999-102207-1.6 selection of isolation transformers a 1:1 isolation transformer is required at the line interface. an isolation transformer with integrated common-mode choke is recommended for exceeding fcc requirements. table 27 gives recommended transformer characteristics. parameter value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min) 350 h 100mv, 100khz, 8ma leakage inductance (max) 0.4 h 1mhz (min) inter-winding capacitance (max) 12pf d.c. resistance (max) 0.9 ? insertion loss (max) 1.0db 0mhz ? 65mhz hipot (min) 1500vrms table 27. transformer selection criteria magnetic manufacturer part number auto mdi-x number of port pulse h1102 yes 1 pulse (low cost) h1260 yes 1 transpower hb726 yes 1 bel fuse s558-5999-u7 yes 1 delta lf8505 yes 1 lankom lf-h41s yes 1 tdk (mag jack) tla-6t718 yes 1 table 28. qualified single port magnetics selection of reference crystal chacteristics value units frequency 25 mhz frequency tolerance (max) 50 ppm load capacitance (max) 20 pf series resistance 25 ? table 29. typical reference crystal characteristics
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 101 m9999-102207-1.6 package information figure 24. 128-pin pqfp package
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 102 m9999-102207-1.6 figure 25. optional 128-pin lqfp package
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 103 m9999-102207-1.6 figure 26. optional 100-ball lfbga package
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 104 m9999-102207-1.6 acronyms and glossary biu bus interface unit the host interface function that performs code conversion, buffering, and the like required for communications to and from a network. bpdu bridge protocol data unit a packet containing ports, addresses, etc. to make sure data being passed through a bridged network arrives at its proper destination. cmos complementary metal oxide semiconductor a common semiconductor manufacturing technique in which positive and negative types of transistors are combined to form a current gate that in turn forms an effective means of controlling electrical current through a chip. crc cyclic redundancy check a common technique for detecting data transmission errors. crc for ethernet is 32 bits long. cut-through switch a switch typically processes received packets by reading in the full packet (storing), then processing the packet to determine where it needs to go, then forwarding it. a cut-through switch simply reads in the first bit of an incoming packet and forwards the packet. cut- through switches do not store the packet. da destination address the address to send packets. dma direct memory access a design in which memory on a chip is controlled independently of the cpu. eeprom electronically erasable programmable read-only memory a design in which memory on a chip can be erased by exposing it to an electrical charge. eisa extended industry standard architecture a bus architecture designed for pcs using 80x86 processors, or an intel 80386, 80486 or pentium microprocessor. eisa buses are 32 bits wide and support multiprocessing. emi electro-magnetic interference a naturally occurring phenomena when the electromagnetic field of one device disrupts, impedes or degrades the electromagnetic field of another device by coming into proximity with it. in computer technology, computer devices are susceptible to emi because electromagnetic fields are a byproduct of passing electricity through a wire. data lines that have not been properly shielded are susceptible to data corruption by emi. fcs frame check sequence see crc. fid frame or filter id specifies the frame identifier. alternately is the filter identifier. igmp internet group management protocol the protocol defined by rfc 1112 for ip multicast transmissions. ipg inter-packet gap a time delay between successive data packets mandated by the network standard for protocol reasons. in ethernet, the medium has to be "silent" (i.e., no data transfer) for a short period of time before a node can consider the network idle and start to transmit. ipg is used to correct timing differences between a transmitter and receiver. during the ipg, no data is transferred, and information in the gap can be discarded or additions inserted without impact on data integrity. isi inter-symbol interference the disruption of transmitted code caused by adjacent pulses affecting or interfering with each other. isa industry standard architecture a bus architecture used in the ibm pc/xt and pc/at. jumbo packet a packet larger than the standard ethernet packet (1500 bytes). large packet sizes allow for more efficient use of bandwidth, lower overhead, less processing, etc. mdi medium dependent interface an ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. mdi provides the standard interface to a particular media (copper or fiber) and is therefore 'media dependent.'
micrel, inc. ksz8841-16/32 mql/mvl/mbl october 2007 105 m9999-102207-1.6 mdi-x medium dependent interface crossover an ethernet port connection that allows networked end stations (i.e., pcs or workstations) to connect to each other using a null-modem, or crossover, cable. for 10/100 full-duplex networks, an end point (such as a computer) and a switch are wired so that each transmitter connects to the far end receiver. when connecting two computers together, a cable that crosses the tx and rx is required to do this. with auto mdi-x, the phy senses the correct tx and rx roles, eliminating any cable confusion. mib management information base the mib comprises the management portion of network devices. this can include things like monitoring traffic levels and faults (statistical), and can also change operating parameters in network nodes (static forwarding addresses). mii media independent interface the mii accesses phy registers as defined in the ieee 802.3 specification. nic network interface card an expansion board inserted into a computer to allow it to be connected to a network. most nics are designed for a particular type of network, protocol, and media, although some can serve multiple networks. npvid non port vlan id the port vlan id value is used as a vlan reference. pll phase-locked loop an electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or reference, signal. a pll ensures that a communication signal is locked on a specific frequency and can also be used to generate, modulate, and demodulate a signal and divide a frequency. pme power management event an occurrence that affects the directing of power to different components of a system. qmu queue management unit manages packet traffic between mac/phy interface and the system host. the qmu has built-in packet memories for receive and transmit functions called txq (transmit queue) and rxq (receive queue). sa source address the address from which information has been sent. tdr time domain reflectometry tdr is used to pinpoint flaws and problems in underground and aerial wire, cabling, and fiber optics. they send a signal down the conductor and measure the time it takes for the signal -- or part of the signal -- to return. utp unshielded twisted pair commonly a cable containing 4 twisted pairs of wires. the wires are twisted in such a manner as to cancel electrical interference generated in each wire, therefore shielding is not required. vlan virtual local area network a configuration of computers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere. micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant inj ury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or systems is a purchaser?s own risk and purchaser a grees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, incorporated.

▲Up To Search▲

Price & Availability of KSZ8841-16MVIL

	To Download KSZ8841-16MVIL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .